Buried shield structures for power semiconductor devices and related fabrication methods
A semiconductor device includes a semiconductor layer structure having a drift region of a first conductivity type and a well region of a second conductivity type above the drift region. A gate is provided on the semiconductor layer structure adjacent the well region. A buried shielding structure of the second conductivity type is provided under the well region and separated from the well region by a portion of the drift region. Related devices and fabrication methods are also discussed.
1 . A semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type above the drift region;
a gate on the semiconductor layer structure adjacent the well region;
at least one contact shielding structure of the second conductivity type vertically extending into the drift region and laterally spaced apart from the gate;
a bottom shielding structure of the second conductivity type under the gate; and
a buried shielding structure of the second conductivity type under the well region and separated therefrom by a portion of the drift region,
wherein the buried shielding structure laterally extends from the bottom shielding structure to the at least one contact shielding structure.
2 . The semiconductor device of claim 1 , wherein the semiconductor layer structure further comprises a gate trench having sidewalls and a bottom surface therebetween extending into the drift region, wherein the gate is in the gate trench, and
wherein the bottom shielding structure of the second conductivity type is under the bottom surface of the gate trench.
3 . The semiconductor device of claim 1 , wherein at least one of the buried shielding structure and the contact shielding structure comprises a material that is different from that of the drift region.
4 . The semiconductor device of claim 3 , wherein the drift region comprises a wide bandgap semiconductor material, and the at least one of the buried shielding structure and the contact shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.
5 . The semiconductor device of claim 1 , wherein the buried shielding structure has a different concentration of dopants of the second conductivity type than the well region.
6 . The semiconductor device of claim 1 , wherein the semiconductor layer structure further comprises:
a substrate, wherein the drift region is on the substrate; and
a drain contact on the substrate opposite the drift region,
wherein the buried shielding structure laterally extends in the drift region between the well region and the drain contact.
7 . The semiconductor device of claim 6 , wherein the semiconductor layer structure further comprises:
a current spreading region of the first conductivity type extending between the well region and the drain contact, wherein the current spreading region comprises a greater dopant concentration than the drift region.
8 . The semiconductor device of claim 6 , wherein the buried shielding structure comprises a pattern including one or more segments that extend in a first lateral direction, and the gate extends in a second lateral direction that is different from the first lateral direction.
9 . The semiconductor device of claim 8 , wherein a respective width of the one or more segments along the second lateral direction is between about 0.1 and 20 microns.
10 . The semiconductor device of claim 8 , wherein the one or more segments of the buried shielding structure and/or the gate provide linear, elliptical, or polygonal shapes in plan view.
11 . The semiconductor device of claim 6 , wherein the gate comprises a first gate of a first transistor in the semiconductor layer structure, and the buried shielding structure comprises a second gate of a second transistor in the semiconductor layer structure.
12 . The semiconductor device of claim 11 , wherein the first and second transistors are electrically coupled in a cascode amplifier configuration.
13 . The semiconductor device of claim 12 , wherein the semiconductor layer structure further comprises a source region of the first conductivity type above the well region, and further comprising:
a source contact on a surface of the semiconductor layer structure opposite the drain contact, wherein the source contact is electrically coupled to the source region and the buried shielding structure.
14 . A semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type above the drift region;
a gate on the semiconductor layer structure adjacent the well region;
a buried shielding structure of the second conductivity type under the well region and separated therefrom by a portion of the drift region; and
a drain contact on the semiconductor layer structure below the drift region,
wherein the buried shielding structure comprises segments that extend in a first lateral direction and the gate extends in a second lateral direction that is different from the first lateral direction,
wherein the segments are laterally spaced apart such that at least a part of an electrical conduction path between the well region and the drain contact laterally extends along the buried shielding structure in the second lateral direction.
15 . A semiconductor device, comprising:
a semiconductor layer structure comprising:
a drift region of a first conductivity type;
a buried shielding structure of a second conductivity type in the drift region;
a well region of the second conductivity type above the drift region; and
a source region of the first conductivity type above the well region; and
a source contact on a surface of the semiconductor layer structure, wherein the source contact is electrically coupled to the source region and to the buried shielding structure,
wherein the source region, the well region, and a first portion of the drift region between the well region and the buried shielding structure provide p-n junctions of a first transistor, and
wherein the first portion of the drift region, the buried shielding structure, and a second portion of the drift region provide p-n junctions of a second transistor.
16 . The semiconductor device of claim 15 ,
wherein the source contact is electrically coupled to the buried shielding structure by at least one contact shielding structure of the second conductivity type.
17 . The semiconductor device of claim 16 , further comprising:
a gate on the semiconductor layer structure adjacent the well region,
wherein the gate comprises a first gate of the first transistor, and the buried shielding structure comprises a second gate of the second transistor.
18 . The semiconductor device of claim 17 , wherein the first and second transistors are electrically coupled in a cascode amplifier configuration.
19 . The semiconductor device of claim 17 , wherein the semiconductor layer structure further comprises:
a gate trench having sidewalls and a bottom surface therebetween extending into the drift region, wherein the gate is in the gate trench, and wherein
a metal layer extends from the source contact along at least one of the sidewalls of the gate trench to contact the buried shielding structure.
20 . A semiconductor device, comprising:
a semiconductor layer structure comprising a first surface and a second surface opposite the first surface;
a gate adjacent the first surface of the semiconductor layer structure;
a drain contact on the second surface of the semiconductor layer structure;
a source contact on the first surface of the semiconductor layer structure, wherein the source contact is electrically coupled to a source region of a first conductivity type and a buried shielding structure of a second conductivity type in the semiconductor layer structure; and
first and second transistors in the semiconductor layer structure and electrically coupled in a cascode amplifier configuration between the first and second surfaces thereof.
21 . The semiconductor device of claim 20 ,
wherein the source contact is electrically coupled to the buried shielding structure by at least one contact shielding structure of the second conductivity type.
22 . The semiconductor device of claim 21 , wherein the semiconductor layer structure comprises:
a drift region of the first conductivity type;
a well region of the second conductivity type above the drift region; and
the source region of the first conductivity type above the well region,
wherein the source region, the well region, and a first portion of the drift region between the well region and the buried shielding structure provide the first transistor, and
wherein the first portion of the drift region, the buried shielding structure, and a second portion of the drift region provide the second transistor.
23 . The semiconductor device of claim 22 , wherein the semiconductor layer structure further comprises:
a gate trench having sidewalls and a bottom surface therebetween extending into the drift region, wherein the gate is in the gate trench, and wherein
a metal layer extends from the source contact along at least one of the sidewalls of the gate trench to contact the buried shielding structure.
24 . A method of fabricating a semiconductor device, the method comprising:
providing a drift region of a first conductivity type;
providing a buried shielding structure of a second conductivity type in the drift region;
providing a well region of the second conductivity type above the drift region and separated from the buried shielding structure, wherein the drift region, the buried shielding structure, and the well region form a semiconductor layer structure;
providing a bottom shielding structure of the second conductivity type;
providing at least one contact shielding structure of the second conductivity type vertically extending into the drift region; and
providing a gate on the semiconductor layer structure adjacent the well region,
wherein the bottom shielding structure is under the gate, the at least one contact shielding structure is laterally spaced apart from the gate, and the buried shielding structure laterally extends from the bottom shielding structure to the at least one contact shielding structure.
25 . The method of claim 24 , wherein the buried shielding structure comprises a pattern including one or more segments that laterally extend in the drift region.
26 . The method of claim 25 , wherein providing the buried shielding structure comprises:
forming a first portion of the drift region by a first epitaxy process;
forming the buried shielding structure in or on the first portion of the drift region; and
forming a second portion of the drift region on the buried shielding structure by a second epitaxy process.
27 . The method of claim 26 , wherein forming the buried shielding structure comprises:
implanting dopants of the second conductivity type into or depositing a material of the second conductivity type on the first portion of the drift region to form the buried shielding structure.
28 . The method of claim 27 , further comprising:
forming a mask pattern on the first portion of the drift region before the implanting or the depositing,
wherein the implanting or the depositing is performed in or on areas of the drift region exposed by the mask pattern to form the pattern of the buried shielding structure.
29 . The method of claim 27 , wherein the implanting or the depositing is performed as a blanket process without a mask pattern, and further comprising:
forming a mask pattern on the first portion of the drift region after the implanting or the depositing; and
performing an etching process on areas of the first portion of the drift region exposed by the mask pattern to form the pattern of the buried shielding structure.
30 . The method of claim 26 , further comprising:
forming a current spreading region comprising a greater concentration of dopants of the first conductivity type in the first portion of the drift region,
wherein the buried shielding structure extends adjacent the current spreading region.
31 . The method of claim 25 , wherein providing the buried shielding structure comprises:
forming a mask pattern on a surface of the drift region; and
implanting dopants of the second conductivity type into areas of the drift region exposed by the mask pattern with an implantation energy corresponding to a predetermined depth below the surface of the drift region to form the pattern of the buried shielding structure.
32 . The method of claim 25 , wherein the semiconductor layer structure comprises a substrate, wherein the drift region is on the substrate, and further comprising:
providing a drain contact on the substrate opposite the drift region, wherein the buried shielding structure laterally extends in the drift region between the well region and the drain contact.
33 . The method of claim 32 , wherein the gate comprises a first gate of a first transistor in the semiconductor layer structure, and the buried shielding structure comprises a second gate of a second transistor in the semiconductor layer structure.
34 . The method of claim 33 , wherein the first and second transistors are electrically coupled in a cascode amplifier configuration.
35 . The method of claim 34 , further comprising:
providing a source region of the first conductivity type above the well region; and
providing a source contact on a surface of the semiconductor layer structure opposite the drain contact, wherein the source contact is electrically coupled to the source region and the buried shielding structure.
36 . The method of claim 35 , wherein providing the gate comprises:
forming a gate trench having sidewalls and a bottom surface therebetween extending into a surface of the semiconductor layer structure through the source region and the well region to a depth of about 0.3 to about 10 microns relative to the surface; and
forming the gate in the gate trench.
37 . The method of claim 36 , wherein the method further comprises:
forming a metal layer extending from the source contact along at least one of the sidewalls of the gate trench to contact the buried shielding structure.
38 . The method of claim 25 , wherein the one or more segments extend in a first lateral direction, the gate extends in a second lateral direction that is different from the first lateral direction, and a respective width of the one or more segments along the second lateral direction is between about 0.1 and 20 microns.
39 . The method of claim 25 , wherein the one or more segments of the buried shielding structure and/or the gate provide linear, elliptical, or polygonal shapes in plan view.
40 . The method of claim 24 , wherein the buried shielding structure has a different concentration of dopants of the second conductivity type than the well region.
41 . The method of claim 24 , wherein the buried shielding structure comprises a material that is different from that of the drift region.