Semiconductor memory structure having drain stressor, source stressor and buried gate and method of manufacturing the same

1 . A semiconductor memory structure, comprising:

a substrate;

a gate structure disposed in the substrate, wherein the gate structure is buried in the substrate;

a first shallow trench isolation (STI) disposed in the substrate;

a second STI disposed in the substrate, wherein the gate structure is disposed between the first STI and the second STI;

a drain stressor disposed in the substrate; and

a source stressor disposed in the substrate,

wherein the drain stressor is disposed between the source stressor and the gate structure;

wherein the source stressor is disposed between the drain stressor and the first STI;

wherein the gate structure, the drain stressor, and the source stressor are disposed between the first STI and the second STI;

wherein each of the first STI and the second STI comprises:

a first liner;

a second liner disposed over the first liner;

a third liner disposed over the second liner; and

a filling layer disposed over the third liner.

2 . The semiconductor memory structure of claim 1 , wherein a topmost surface of the first liner is lower than a top surface of the substrate.

3 . The semiconductor memory structure of claim 2 , wherein the second liner comprises an upper portion and a lower portion,

wherein the upper portion of the second liner is in contact with the substrate, the topmost surface of the first liner, the lower portion of the second liner, and the third liner.

4 . The semiconductor memory structure of claim 3 , wherein a width of the upper portion of the second liner is greater than a width of the lower portion of the second liner.

5 . The semiconductor memory structure of claim 1 , wherein a material of the filling layer is different from a material of the second liner and a material of the third liner.

6 . The semiconductor memory structure of claim 1 , wherein the substrate comprises silicon germanium, and the drain stressor and the source stressor comprise silicon.

7 . A semiconductor memory structure, comprising:

a substrate;

a gate structure disposed in the substrate, wherein the gate structure is buried in the substrate;

a first shallow trench isolation (STI) disposed in the substrate;

a second STI disposed in the substrate, wherein the gate structure is disposed between the first STI and the second STI;

a drain stressor disposed in the substrate; and

a source stressor disposed in the substrate,

wherein the drain stressor is disposed between the source stressor and the gate structure;

wherein the source stressor is disposed between the drain stressor and the first STI;

wherein the gate structure, the drain stressor, and the source stressor are disposed between the first STI and the second STI;

wherein the drain stressor comprises:

a first drain layer;

a second drain layer disposed over the first drain layer; and

a third drain layer disposed over the second drain layer.

8 . The semiconductor memory structure of claim 7 , wherein the third drain layer is protruding from the substrate.

9 . A semiconductor memory structure, comprising:

a substrate;

a gate structure disposed in the substrate, wherein the gate structure is buried in the substrate;

a first shallow trench isolation (STI) disposed in the substrate;

a second STI disposed in the substrate, wherein the gate structure is disposed between the first STI and the second STI;

a drain stressor disposed in the substrate; and

a source stressor disposed in the substrate,

wherein the drain stressor is disposed between the source stressor and the gate structure;

wherein the source stressor is disposed between the drain stressor and the first STI;

wherein the gate structure, the drain stressor, and the source stressor are disposed between the first STI and the second STI;

wherein the source stressor comprises:

a first source layer;

a second source layer disposed over the first source layer; and

a third source layer disposed over the second source layer.

10 . The semiconductor memory structure of claim 9 , wherein the third source layer is protruding from the substrate.