Semiconductor device having gate insulating layer in trench and on upper surface of substrate, channel layer on gate insulating layer, and spaced-apart source and drain electrodes on channel layer

1 . A semiconductor device, comprising:

a substrate including a gate electrode therein, one or more inner surfaces of the substrate at least partially defining a trench penetrating the gate electrode and in the substrate;

a gate insulating layer that is both in the trench and on an upper surface of the substrate;

a channel layer on the gate insulating layer, the channel layer including a two-dimensional (2D) semiconductor material; and

a source electrode and a drain electrode, which are spaced apart from each other on the channel layer.

2 . The semiconductor device of claim 1 , wherein a width in a horizontal direction of an upper area of the trench that is proximate to the upper surface of the substrate is different from a width in the horizontal direction of a lower area of the trench that is distal from the upper surface of the substrate, the horizontal direction extending parallel to the upper surface of the substrate.

3 . The semiconductor device of claim 1 , wherein a width of the trench in a horizontal direction extending parallel to the upper surface of the substrate continuously changes from a first width proximate to the upper surface of the substrate towards a second width proximate to an interior of the substrate in a vertical direction extending perpendicular to the upper surface of the substrate.

4 . The semiconductor device of claim 1 , wherein a width of the trench in a horizontal direction extending parallel to the upper surface of the substrate continuously increases from a first width proximate to the upper surface of the substrate towards a second width proximate to an interior of the substrate in a vertical direction extending perpendicular to the upper surface of the substrate.

5 . The semiconductor device of claim 1 , wherein an inclination angle of a wall of the trench to a central axis of the semiconductor device is greater than 0° and less than or equal to 45°.

6 . The semiconductor device of claim 1 , wherein the source electrode is in the trench, and the drain electrode is on the upper surface of the substrate.

7 . The semiconductor device of claim 1 , wherein a distance between the source electrode and the drain electrode in a horizontal direction parallel to the upper surface of the substrate is smaller than a distance between the source electrode and the gate electrode in the horizontal direction.

8 . The semiconductor device of claim 1 , wherein a distance between the source electrode and the drain electrode in a horizontal direction parallel to the upper surface of the substrate is 0 nm.

9 . The semiconductor device of claim 1 , wherein at least one of the source electrode or the drain electrode has a central axis that is coaxial with a central axis of the semiconductor device so as to be symmetric with respect to the central axis of the semiconductor device.

10 . The semiconductor device of claim 1 , wherein

the gate electrode comprises a first gate electrode and a second gate electrode, which are spaced apart from each other, and

the drain electrode comprises a first drain electrode and a second drain electrode, which are on separate, respective areas of the upper surface of the substrate that at least partially overlap separate, respective ones of the first gate electrode and the second gate electrode in a vertical direction extending perpendicular to the upper surface of the substrate.

11 . The semiconductor device of claim 1 , wherein the 2D semiconductor material includes transition metal dichalcogenide (TMD).

12 . The semiconductor device of claim 11 , wherein the TMD includes

a metallic element selected from Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and

a chalcogen element selected from S, Se, and Te.

13 . The semiconductor device of claim 1 , wherein the gate electrode includes at least one of graphene, amorphous carbon, Cu, Au, Ag, Mo, W, Ti, Al, Co, Ru, TiN, or indium tin oxide.

14 . A method of manufacturing a semiconductor device, the method comprising:

preparing a substrate including a gate electrode therein;

forming, in the substrate, a trench at least partially defined by one or more inner surfaces of the substrate such that the trench penetrates the gate electrode;

forming a gate insulating layer that is both in the trench and on an upper surface of the substrate;

forming, on the gate insulating layer, a channel layer including a two-dimensional (2D) semiconductor material; and

forming a source electrode and a drain electrode that are spaced apart from each other on the channel layer.

15 . The method of claim 14 , wherein the channel layer is formed based on using a vapor deposition process.

16 . The method of claim 15 , wherein the vapor deposition process includes at least one of metal organic chemical vapor deposition (MOCVD), thermal chemical vapor deposition (TCVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

17 . The method of claim 14 , wherein an inclination angle of a wall of the trench to a central axis of the semiconductor device is greater than 0° and less than or equal to 45°.

18 . The method of claim 14 , wherein the source electrode and the drain electrode are formed based on using physical vapor deposition (PVD).

19 . The method of claim 14 , wherein a width in a horizontal direction of an upper area of the trench that is proximate to the upper surface of the substrate is different from a width in the horizontal direction of a lower area of the trench that is distal from the upper surface of the substrate, the horizontal direction extending parallel to the upper surface of the substrate.

20 . The method of claim 14 , wherein the 2D semiconductor material includes transition metal dichalcogenide (TMD).