Pillar structure and super junction semiconductor device including the same
A pillar structure includes an epitaxial layer of a first conductivity type including an active region and a peripheral region surrounding the active region and a plurality of pillars of a second conductivity type, the pillars extending in a vertical direction within the epitaxial layer, being spaced apart from each other in a horizontal direction, respectively, and including active pillars provided in the active region and peripheral pillars provided in the peripheral region, wherein the active pillars are spaced apart from another adjacent each other at a first pitch, and a pair of the peripheral pillars are branched from one of the active pillars and are spaced apart from each other at a second pitch smaller than the first pitch.
1 . A pillar structure comprising:
an epitaxial layer of a first conductivity type including an active region and a peripheral region surrounding the active region; and
a plurality of pillars of a second conductivity type, the pillars extending in a vertical direction within the epitaxial layer, being spaced apart from each other in a horizontal direction, respectively, and including active pillars provided in the active region and peripheral pillars provided in the peripheral region,
wherein the peripheral pillars comprise lower peripheral pillars arranged at a first pitch, and a pair of upper peripheral pillars,
wherein the pair of upper peripheral pillars are branched from one of the lower peripheral pillars and are spaced apart from each other at a second pitch,
wherein the second pitch is smaller than the first pitch and is maintained constant in the vertical direction.
2 . The pillar structure of claim 1 , wherein the peripheral region has an elliptical band shape, and the pair of the peripheral pillars are arranged selectively in a longitudinal region of the peripheral region.
3 . The pillar structure of claim 1 , wherein the second pitch is ½ times the first pitch.
4 . The pillar structure of claim 3 , wherein the upper peripheral pillar portion has a second width being ½ times a first width of each of the active pillars.
5 . The pillar structure of claim 1 , wherein the pair of the peripheral pillars and the one of
the active pillars are connected to one another in a “Y” shape when viewed in a plan view.
6 . The pillar structure of claim 1 , wherein each of the active pillars includes a plurality of spherical filler cells having a first diameter.
7 . The pillar structure of claim 6 , wherein each of the active cells has a first diameter of a spherical shape.
8 . The pillar structure of claim 7 , wherein each of the peripheral pillars includes a lower 10 peripheral portion having a plurality of lower peripheral cells stacked in the vertical direction, each having the first diameter of the spherical shape, and an upper peripheral porting having a plurality of upper peripheral cells being connected to a topmost one of the lower peripheral cells, each having a second diameter of spherical shape smaller than the first diameter.
9 . A super junction semiconductor device comprising:
a substrate of a first conductive type, the substrate including an active region, a peripheral region surrounding the active region and a transition region interposed between the active region the peripheral region;
an epitaxial layer disposed on the substrate, the epitaxial layer having the first 20 conductive type;
a plurality of pillars extending in a vertical direction, each being spaced apart from each other in a horizontal direction within the epitaxial layer, and including active pillars
provided in the active region and peripheral pillars provided in the peripheral region;
gate structures disposed on the epitaxial layer in the active region, and each extending across the epitaxial layer and the pillars in a horizontal direction; and
a gate pad disposed on the epitaxial layer in the transition region, and being electrically connected to the gate structures,
wherein the peripheral pillars comprise lower peripheral pillars arranged at a first pitch, and a pair of upper peripheral pillars,
wherein the pair of upper peripheral pillars are branched from one of the lower peripheral pillars and are spaced apart from each other at a second pitch,
wherein the second pitch is smaller than the first pitch and is maintained constant in the vertical direction.
10 . The super junction semiconductor device of claim 9 , wherein the peripheral region has an elliptical band shape, and a plurality of upper peripheral pillar portion is arranged in the second pitch and selectively in a longitudinal region of the peripheral region.
11 . The super junction semiconductor device of claim 9 , wherein the second pitch is ½ times the first pitch.
12 . The super junction semiconductor device of claim 9 , wherein the upper peripheral pillar portion has a second width being smaller than a first width of each of the active pillars.
13 . The super junction semiconductor device of claim 9 , wherein the second width is ½ times the first width of each of the active pillars.
14 . The super junction semiconductor device of claim 9 , wherein the pair of the peripheral pillars and the one of the active pillars are connected to one another in a “Y” shape when viewed in a plan view.
15 . The super junction semiconductor device of claim 9 , wherein the pair of the 5 peripheral pillar and the one of the active pillars are connected to one another in a ‘C” shape when viewed in a plan view.
16 . The super junction semiconductor device of claim 9 , wherein each of the active pillars includes a plurality of active cells stacked in the vertical direction.
17 . The super junction semiconductor device of claim 16 , wherein each of the active cells has a first diameter of a spherical shape.
18 . The super junction semiconductor device of claim 17 , wherein each of the peripheral 15 pillars includes a plurality of lower peripheral cells stacked in the vertical direction, each having of a first diameter of a spherical shape, and a plurality of upper peripheral cells being connected to a topmost one of the lower peripheral cells, each having a second diameter of spherical shape smaller than the first diameter.
19 . The super junction semiconductor device of claim 18 , wherein the upper peripheral cells are stacked at least with two cells.