Multiple-depth trench isolation for electrostatic discharge protection devices
Structures including an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate having a top surface, an electrostatic discharge protection device including a base in the semiconductor substrate, and first and second trench isolation regions disposed in the base of the electrostatic discharge protection device. The first trench isolation region extends from the top surface of the semiconductor substrate to a first depth in the base, the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth greater than the first depth.
1 . A structure comprising:
a semiconductor substrate having a top surface;
an electrostatic discharge protection device including a base in the semiconductor substrate;
a first trench isolation region disposed in the base of the electrostatic discharge protection device, the first trench isolation region extending from the top surface of the semiconductor substrate to a first depth in the base; and
a second trench isolation region disposed in the base of the electrostatic discharge protection device, the second trench isolation region extending from the top surface of the semiconductor substrate to a second depth in the base, and the second depth greater than the first depth.
2 . The structure of claim 1 wherein the electrostatic discharge protection device includes a collector in the semiconductor substrate and an emitter in the semiconductor substrate, the collector and the emitter have a first conductivity type, and the base has a second conductivity type opposite from the first conductivity type.
3 . The structure of claim 2 wherein the second trench isolation region surrounds the emitter.
4 . The structure of claim 3 wherein the first trench isolation region surrounds the emitter, and the second trench isolation region penetrates through a portion of the first trench isolation region into the base.
5 . The structure of claim 2 further comprising:
a third trench isolation region disposed in the semiconductor substrate, the third trench isolation region extending from the top surface of the semiconductor substrate to a third depth that is greater than the second depth.
6 . The structure of claim 5 wherein the third trench isolation region surrounds the emitter, the base, the first trench isolation region, and the second trench isolation region.
7 . The structure of claim 6 further comprising:
a fourth trench isolation region disposed in the semiconductor substrate, the fourth trench isolation region extending from the top surface of the semiconductor substrate to a fourth depth that is greater than the third depth.
8 . The structure of claim 7 wherein the fourth trench isolation region surrounds the collector, the emitter, the base, the first trench isolation region, and the second trench isolation region.
9 . The structure of claim 1 further comprising:
a third trench isolation region disposed in the semiconductor substrate, the third trench isolation region extending from the top surface of the semiconductor substrate to the second depth in the base.
10 . The structure of claim 9 wherein the electrostatic discharge protection device includes a collector in the semiconductor substrate and an emitter in the semiconductor substrate, the collector and the emitter have a first conductivity type, the base has a second conductivity type opposite from the first conductivity type, and the second trench isolation region and the third trench isolation region surround the emitter.
11 . The structure of claim 10 wherein the first trench isolation region surrounds the emitter, the second trench isolation region extends through a first portion of the first trench isolation region into the base, and the third trench isolation region penetrates through a second portion of the first trench isolation region into the base.
12 . The structure of claim 9 wherein the base wraps around the second trench isolation region and the third trench isolation region.
13 . The structure of claim 9 further comprising:
a fourth trench isolation region disposed in the semiconductor substrate, the fourth trench isolation region extending from the top surface of the semiconductor substrate to the second depth in the base.
14 . The structure of claim 1 wherein the second trench isolation region penetrates partially through the base.
15 . The structure of claim 1 further comprising:
a third trench isolation region positioned in the semiconductor substrate, the third trench isolation region surrounding the base, the first trench isolation region, and the second trench isolation region, and the third trench isolation region extending to a third depth in the semiconductor substrate that is greater than the second depth.
16 . The structure of claim 15 wherein the electrostatic discharge protection device includes a collector in the semiconductor substrate and an emitter in the semiconductor substrate, the collector and the emitter has a first conductivity type, and the base has a second conductivity type opposite from the first conductivity type.
17 . The structure of claim 16 wherein the second trench isolation region surrounds the emitter, and the third trench isolation region surrounds the emitter and the collector.
18 . The structure of claim 1 wherein the second trench isolation region penetrates through a portion of the first trench isolation region into the base.
19 . The structure of claim 1 wherein the base wraps around the first trench isolation region.
20 . A method comprising:
forming an electrostatic discharge protection device including a base in a semiconductor substrate;
forming a first trench isolation region disposed in the base of the electrostatic discharge protection device; and
forming a second trench isolation region disposed in the base of the electrostatic discharge protection device,
wherein the first trench isolation region extends from a top surface of the semiconductor substrate to a first depth in the base, the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth is greater than the first depth.