Method of 3D epitaxial growth for high density 3D horizontal nanosheets
Techniques herein include methods of forming channel structures for field effect transistors having a channel current path parallel to a surface of a substrate. 3D in-situ horizontal or lateral growth of the channel and source/drain regions allows for a custom doping in the 3D horizontal nanosheet direction for NMOS and PMOS devices. An ultra-short channel length is achieved with techniques herein because the channel is epitaxially grown in the 3D horizontal nanosheet direction at the monolayer level. Since the channel is grown in a dielectric cavity, a precise channel cross sectional area can be tuned.
1 . A method of fabricating a semiconductor device, comprising:
forming a mixed layer stack on a surface of a substrate including a semiconductor material, the mixed layer stack including
a multilayer dielectric layer stack surrounding a multilayer epitaxial layer stack, the multilayer dielectric layer stack including a plurality of alternating dielectric layers alternating in a direction perpendicular to a plane of the surface of the substrate, the plurality of dielectric layers having at least two different dielectric materials having different etch selectivities to one another, a first dielectric layer of the plurality of dielectric layers comprising a first dielectric material of the at least two different dielectric materials, the first dielectric layer of the plurality of dielectric layers having a thickness corresponding to a first channel thickness, and
the multilayer epitaxial layer stack surrounded by the multilayer dielectric layer stack on the surface of the substrate, the multilayer epitaxial layer stack including a plurality of alternating epitaxial layers alternating in the direction perpendicular to the plane of the surface of the substrate, the plurality of epitaxial layers having at least two different epitaxial materials having different etch selectivities to one another, a first epitaxial layer of the plurality of epitaxial layers comprising a first epitaxial material of the at least two different epitaxial materials, the first dielectric layer of the plurality of dielectric layers being substantially aligned with and forming an interface with the first epitaxial layer of the plurality of epitaxial layers along the direction parallel to the plane of the surface of the substrate;
removing the first dielectric material from the first dielectric layer to uncover the interface with the first epitaxial layer and forming an opening in the multilayer dielectric layer stack, a direction of the opening being parallel with the surface of the substrate;
growing a channel structure including a channel material laterally within the opening via epitaxial growth using the uncovered interface with the first epitaxial layer and the first epitaxial material as a seed material, the first epitaxial layer and the first epitaxial material at the interface comprising a first source/drain region; and
growing, at an end of the channel structure opposite the first source/drain region and the interface, a second source/drain region via epitaxial growth using the end of the channel structure as the seed material.
2 . The method of claim 1 , wherein the growing the channel structure including the channel material within the opening via epitaxial growth further comprises growing the channel structure beyond a width of the first dielectric material in the first dielectric layer that was removed.
3 . The method of claim 2 , wherein the growing the channel structure including the channel material within the opening via epitaxial growth further comprises performing a directional etch to remove the channel structure grown beyond the width of the first dielectric material in the first dielectric layer that was removed to align an end of the channel structure with an edge of the multilayer dielectric layer stack, a length of the channel being the same as the width of the first dielectric material in the first dielectric layer that was removed.
4 . The method of claim 2 , wherein the growing the channel structure including the channel material within the opening via epitaxial growth further comprises performing the epitaxial growth until a predetermined length of the channel structure is reached.
5 . The method of claim 1 , wherein the growing the second source/drain region via epitaxial growth further comprises performing the epitaxial growth until a predetermined length of the second source/drain region is reached.
6 . The method of claim 1 , wherein the removing the first dielectric material from the first dielectric layer to uncover the interface with the first epitaxial layer further comprises
depositing a fill around the mixed layer stack; and
patterning an etch mask over top the mixed layer stack, a pattern of the etch mask covering the mixed layer stack while including an overhang on a first side of the mixed layer stack and no overhang on a second side of the mixed layer stack, the overhang configured to cover a portion of the fill adjacent to the first side of the mixed layer stack and leave the fill disposed adjacent to the first side of the mixed layer stack after the etch.
7 . The method of claim 6 , wherein the fill comprises a dielectric material having etch selectivity to the at least two different dielectric materials included in the multilayer dielectric layer stack.
8 . The method of claim 1 , further comprising
depositing a dielectric fill to cover the second source/drain region, the dielectric fill comprising a dielectric material having etch selectivity to the at least two different dielectric materials included in the multilayer dielectric layer stack;
patterning an etch mask over top the mixed layer stack and the dielectric fill, a pattern of the etch mask not covering portions of the mixed layer stack where the channel structure is disposed below; and
removing a second dielectric material of the at least two different dielectric materials from the portions of the mixed layer stack not covered by the etch mask to uncover the channel structure.
9 . The method of claim 8 , further comprising forming gate-all-around (GAA) structures around the channel structure to form a gate electrode via a selective high-k material deposition and a selective metal gate electrode deposition on the channel structure.
10 . The method of claim 9 , wherein
the mixed layer stack includes at least five layers,
at least two transistor devices are formed including the first source/drain region, the channel structure, and the second source/drain region, and
the at least two transistor devices are separated by a layer comprising the second dielectric material aligned vertically with the dielectric multilayer stack and a dielectric material aligned vertically with the multilayer epitaxial layer stack, the dielectric material being etch selective to the at least two dielectric materials and the dielectric fill.