Semiconductor device structure and method for forming the same
A semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate. The structure also includes gate structures that are wrapped around the first nanostructures and the second nanostructures and that extend along a first direction. The structure also includes a dielectric structure formed between two of the gate structures and parallel to the gate structures. A first sidewall of the first nanostructures is shifted from a first sidewall of the second nanostructures in a second direction, the second direction is different from the first direction.
1 . A semiconductor device structure, comprising:
first nanostructures and second nanostructures formed over a substrate;
gate structures wrapped around the first nanostructures and the second nanostructures and extending along a first direction; and
a dielectric structure formed between two of the gate structures and parallel to the gate structures,
wherein a first sidewall of the first nanostructures is shifted from a first sidewall of the second nanostructures in a second direction, and wherein the second direction is different from the first direction.
2 . The semiconductor device structure as claimed in claim 1 , wherein the dielectric structure is sandwiched between the first nanostructures and the second nanostructures.
3 . The semiconductor device structure as claimed in claim 1 , further comprising:
a wall structure formed beside the first nanostructures,
wherein the dielectric structure is formed across the wall structure.
4 . The semiconductor device structure as claimed in claim 3 , wherein the wall structure is in contact with a bottom surface and sidewalls of a bottom portion of the dielectric structure.
5 . The semiconductor device structure as claimed in claim 3 , wherein the wall structure protrudes from a third sidewall of the second nanostructures in the first direction in a top view.
6 . The semiconductor device structure as claimed in claim 3 , further comprising:
a second dielectric structure parallel to the dielectric structure formed across the second nanostructures.
7 . The semiconductor device structure as claimed in claim 6 , wherein one of the gate structures is formed between the dielectric structure and the second dielectric structure.
8 . The semiconductor device structure as claimed in claim 3 , further comprising:
a second wall structure formed beside the second nanostructures,
wherein the second wall structure is shifted from the wall structure.
9 . A semiconductor device structure, comprising:
a wall structure formed over a substrate;
first nanostructures attached to a first sidewall of the wall structure;
second nanostructures formed parallel to the first nanostructures;
third nanostructures formed parallel to the first nanostructures and the second nanostructures and attached to a second sidewall of the wall structure;
a dielectric structure sandwiched between the first nanostructures and the second nanostructures; and
gate structures formed across the first nanostructures and the second nanostructures,
wherein the first nanostructures and the second nanostructures have different widths.
10 . The semiconductor device structure as claimed in claim 9 , further comprising:
an isolation structure formed beside the second nanostructures,
wherein the wall structure and the isolation structure are at opposite sides of the dielectric structure.
11 . The semiconductor device structure as claimed in claim 9 , further comprising:
a first seam formed in the wall structure,
wherein a portion of the dielectric structure is exposed by the first seam.
12 . The semiconductor device structure as claimed in claim 11 , further comprising:
a second seam formed in the dielectric structure,
wherein the second seam is separated from the first seam.
13 . The semiconductor device structure as claimed in claim 9 , wherein the dielectric structure partially overlaps the wall structure.
14 . The semiconductor device structure as claimed in claim 9 , further comprising:
source/drain structures formed at opposite sides of the gate structures; and
a dummy gate material formed between the source/drain structures and the dielectric structure.
15 . The semiconductor device structure as claimed in claim 9 , wherein a bottom surface of the dielectric structure is lower than a top surface of the wall structure.
16 . A semiconductor device structure, comprising:
an isolation structure surrounding a substrate;
first nanostructures and second nanostructures over the substrate;
gate structures wrapped around the first nanostructures and the second nanostructures;
a dielectric structure between the first nanostructures and the second nanostructures, wherein a lower portion of the dielectric structure extends into the isolation structure; and
a wall structure attached to the first nanostructures, wherein the wall structure is at opposite sides of the dielectric structure.
17 . The semiconductor device structure as claimed in claim 16 , wherein a bottom width of the dielectric structure is less than a top width of the dielectric structure.
18 . The semiconductor device structure as claimed in claim 16 , wherein an area of the wall structure on a first side of the dielectric structure is greater than an area of the wall structure on a second side of the dielectric structure opposite to the first side in a top view.
19 . The semiconductor device structure as claimed in claim 16 , wherein the first nanostructures and the second nanostructures have different widths.
20 . The semiconductor device structure as claimed in claim 16 , wherein the lower portion of the dielectric structure has a tapered width.