Buried near-gate local interconnects and methods of their manufacture

1 . A method for fabricating a semiconductor device, the method comprising:

forming a conductive material layer on a semiconductor device, the semiconductor device comprising at least two gate structures and at least two source/drain surfaces of at least two source/drain regions, wherein an interlevel dielectric layer separates each of the at least two gate structures from each of the at least two source/drain surfaces, wherein the conductive material layer extends through openings of the interlevel dielectric layer, contacts the at least two source/drain surfaces and forms at least two conductive material interconnects, and wherein the conductive material layer extends over the interlevel dielectric layer;

forming an interconnect mask over portions of the conductive material layer, wherein the conductive material layer comprises an up-via, wherein the conductive material layer is formed over a portion of the interlevel dielectric layer between neighboring conductive material interconnects and the interconnect mask is formed over portions of the conductive material layer adjacent to the neighboring conductive material interconnects, and the conductive material layer between the neighboring conductive material interconnects is exposed; and

forming an interconnect by subtractively etching a portion of the conductive material layer, exposed through the interconnect mask.

2 . The method of claim 1 , further comprising forming an ultra-low-k dielectric layer above the interconnect.

3 . The method of claim 2 , wherein the ultra-low-k dielectric layer is coplanar with a portion of each of the at least two conductive material interconnects.

4 . A method for fabricating a semiconductor device, the method comprising:

forming a conductive material layer on a semiconductor device, the semiconductor device comprising at least two gate structures and at least two source/drain surfaces of at least two source/drain regions, wherein an interlevel dielectric layer separates each of the at least two gate structures from each of the at least two source/drain surfaces, wherein the conductive material layer extends through openings of the interlevel dielectric layer, contacts the at least two source/drain surfaces and forms at least two conductive material interconnects, and wherein the conductive material layer extends over the interlevel dielectric layer in a direction substantially perpendicular to the at least two gate structures;

forming an interconnect mask over portions of the conductive material layer, wherein the conductive material layer comprises an up-via, and the conductive material layer between the portions of the conductive material layer are exposed; and

forming an interconnect by subtractively etching a portion of the conductive material layer, exposed through the interconnect mask.

5 . A method for fabricating a semiconductor device, the method comprising:

forming a conductive material layer on a semiconductor device, the semiconductor device comprising at least three gate structures and at least three source/drain surfaces of at least three source/drain regions, wherein an interlevel dielectric layer separates each of the at least three gate structures from each of the at least three source/drain surfaces, wherein the conductive material layer extends through openings of the interlevel dielectric layer, contacts the at least three source/drain surfaces and forms at least three conductive material interconnects, and wherein the conductive material layer extends over the interlevel dielectric layer, between at least three conductive material interconnects;

forming a conductive material mask on the conductive material layer over a first source/drain surface of the at least three conductive material interconnects, on the conductive material layer over a second conductive material interconnect of the at least three conductive material interconnects, on the conductive material layer over a third conductive material interconnect of the at least three conductive material interconnects, and on the conductive material layer above the interlevel dielectric layer, between the first conductive material interconnect and the second conductive material interconnect;

forming an interconnect mask over portions of the conductive material layer, wherein the conductive material layer comprises an up-via; and

forming an interconnect by subtractively etching a portion of the conductive material layer, exposed through the interconnect mask.

6 . The method of claim 5 , further comprising: subtractively etching the conductive material layer between the third conductive material interconnect and the second conductive material interconnect, exposing the interlevel dielectric layer between the third conductive material interconnect and the second conductive material interconnect.

7 . The method of claim 6 , further comprising:

forming the interconnect mask over the conductive material layer above the third conductive material interconnect, the exposed interlevel dielectric layer between the third conductive material interconnect and the second conductive material interconnect, the conductive material layer over the second conductive material interconnect, and the conductive material layer over the first conductive material interconnect, wherein the conductive material layer between the first conductive material interconnect and the second conductive material interconnect comprises the up-via.

8 . The method of claim 7 , further comprising:

forming the interconnect by subtractively etching the portion of the conductive material layer extended over the interlevel dielectric layer, between the first conductive material interconnect and the second conductive material interconnect.

9 . The method of claim 8 , further comprising the step of forming an ultra-low-k dielectric layer above the interconnect.

10 . The method of claim 8 , further comprising the step of forming an ultra-low-k dielectric layer on the interlevel dielectric layer between the second source/drain surface and the third source/drain surface.

11 . The method of claim 10 , wherein the ultra-low-k dielectric layer above the interconnect is coplanar with the ultra-low-k dielectric layer on the interlevel dielectric layer between the second source/drain surface and the third source/drain surface.