Semiconductor structure and fabricating method of the same

1 . A semiconductor structure, comprising:

a substrate;

a gate structure disposed on the substrate;

a liner oxide contacting a side of the gate structure;

a silicon oxide spacer contacting the liner oxide, wherein an end of the silicon oxide spacer forms a kink profile;

a silicon nitride spacer contacting the silicon oxide spacer, wherein a tail of the silicon nitride spacer covers part of the kink profile; and

a stressor covering the silicon nitride spacer and the substrate.

2 . The semiconductor structure of claim 1 , wherein the substrate at one side of the gate structure comprises a concave and convex surface, and the kink profile contacts and covers the concave and convex surface.

3 . The semiconductor structure of claim 1 , wherein a surface of the tail and a surface of the kink profile together form a non-pointed surface.

4 . The semiconductor structure of claim 1 , wherein the silicon nitride spacer is divided into a top part, a middle part and a bottom part, and the top part is farther away from the substrate, the bottom part is closer to the substrate, the middle part is located between the top part and the bottom part, and the tail extends from the bottom part.

5 . The semiconductor structure of claim 4 , wherein a direction is parallel to a surface of the substrate directly below the gate structure, the top part comprises a first thickness, the middle part comprises a second thickness, the bottom part comprises a third thickness, the first thickness, the second thickness and the third thickness are all along the direction, the first thickness is smaller than the second thickness, and the third thickness is not smaller than the second thickness.

6 . The semiconductor structure of claim 5 , wherein the third thickness is greater than the second thickness.

7 . The semiconductor structure of claim 1 , further comprising:

two lightly doping regions respectively disposed in the substrate at two sides of the gate structure;

a source and a drain respectively disposed in the substrate at two sides of the gate structure;

two silicides respectively disposed on the source and the drain, wherein the stressor contacts the two silicides; and

two conductive plugs penetrating the stressor and respectively contacting each of the two silicides.

8 . The semiconductor structure of claim 1 , wherein the gate structure comprises:

a gate dielectric layer contacting the substrate; and

a metal gate disposed on the gate dielectric layer.

9 . A fabricating method of a semiconductor structure, comprising:

providing a substrate;

forming a gate structure disposed on the substrate;

forming a liner oxide contacting a side of the gate structure;

forming a silicon oxide spacer contacting the liner oxide, wherein an end of the silicon oxide spacer forms a kink profile;

forming a silicon nitride spacer contacting the silicon oxide spacer, wherein a tail of the silicon nitride spacer covers part of the kink profile; and

forming a stressor covering the silicon nitride spacer and the substrate.

10 . The fabricating method of a semiconductor structure of claim 9 , wherein steps of fabricating the silicon nitride spacer comprise:

forming a first silicon nitride spacer;

performing a dry etching to etch the first silicon nitride spacer; and

after the dry etching, performing a wet etching to etch the first silicon nitride spacer to form the silicon nitride spacer.

11 . The fabricating method of a semiconductor structure of claim 10 , further comprising:

before performing the dry etching, performing a first ion implantation process to form a source and a drain in the substrate at two sides of the gate structure;

before performing the dry etching, forming two silicides respectively disposed on the source and the drain, wherein the stressor contacts the two silicides; and

after forming the stressor, forming two conductive plugs to penetrate the stressor and respectively contact the source and the drain.

12 . The fabricating method of a semiconductor structure of claim 10 , wherein the dry etching comprises using CF 4 or CH 3 F as etchant gas.

13 . The fabricating method of a semiconductor structure of claim 10 , wherein the wet etching comprises performing the wet etching by using phosphoric acid aqueous solution at a temperature between 80° C. and 150° C., and a concentration of the phosphoric acid aqueous solution is between 50% and 85%.

14 . The fabricating method of a semiconductor structure of claim 9 , further comprising after forming the liner oxide and before forming the silicon oxide spacer, performing a second ion implantation process, wherein the second ion implantation process comprises:

implanting dopants to form two lightly doping regions in the substrate at two sides of the gate structure by taking the gate structure and the silicon oxide spacer as a mask, wherein during the second ion implantation process, the surface of the substrate is bombarded to form a concave and convex surface, and the silicon oxide spacer contacting the concave and convex surface forms the kink profile.

15 . The fabricating method of a semiconductor structure of claim 9 , wherein a surface of the tail and a surface of the kink profile together form a non-pointed surface.

16 . The fabricating method of a semiconductor structure of claim 9 , wherein the silicon nitride spacer is divided into a top part, a middle part and a bottom part, and the top part is farther away from the substrate, the bottom part is closer to the substrate, the middle part is located between the top part and the bottom part, and the tail extends from the bottom part.

17 . The fabricating method of a semiconductor structure of claim 16 , wherein a direction is parallel to a surface of the substrate directly below the gate structure, the top part comprises a first thickness, the middle part comprises a second thickness, the bottom part comprises a third thickness, the first thickness, the second thickness and the third thickness are all along the direction, the first thickness is smaller than the second thickness, and the third thickness is not smaller than the second thickness.

18 . The fabricating method of a semiconductor structure of claim 17 , wherein the third thickness is greater than the second thickness.

19 . The fabricating method of a semiconductor structure of claim 9 , wherein the gate structure comprises:

a gate dielectric layer contacting the substrate; and

a metal gate disposed on the gate dielectric layer.