Vertical transport transistor devices with back side interconnects

1 . A semiconductor structure comprising:

a first vertical transistor;

a second vertical transistor;

a first contact connecting to a source/drain region at a first side of the first vertical transistor;

a second contact extending from the first side of the first vertical transistor to a second side of the first vertical transistor;

a third contact connecting to a source/drain region at a first side of the second vertical transistor;

a fourth contact extending from the first side of the second vertical transistor to a second side of the second vertical transistor;

a first interconnect structure at the first side of the first vertical transistor connecting the first contact to the second contact; and

a second interconnect structure at the first side of the second vertical transistor connecting the third contact to the fourth contact;

wherein the second contact and the fourth contact are disposed in a region between the first vertical transistor and the second vertical transistor.

2 . The semiconductor structure of claim 1 , wherein the second contact connects to one or more back-end-of-line interconnects at the second side of the first vertical transistor.

3 . The semiconductor structure of claim 1 , wherein the first contact is confined by one or more shallow trench isolation region structures.

4 . The semiconductor structure of claim 1 , wherein the second contact and the fourth contact are in a dummy fin region on one side of (i) a first fin region providing a channel for the first vertical transistor and (ii) a second fin region providing a channel for the second vertical transistor.

5 . The semiconductor structure of claim 1 , further comprising an interlayer dielectric layer surrounding the first contact.

6 . The semiconductor structure of claim 5 , further comprising a fifth contact disposed in the interlayer dielectric layer connecting to a source/drain region at the first side of the second vertical transistor, the fifth contact connecting to a power distribution network at the first side of the second vertical transistor.

7 . A semiconductor structure comprising:

a vertical transistor;

a first contact connecting to a source/drain region at a first side of the vertical transistor;

a second contact extending from the first side of the vertical transistor to a second side of the vertical transistor; and

an interconnect structure at the first side of the vertical transistor connecting the first contact to the second contact;

wherein the second contact is in a dummy fin region between (i) a first fin region providing a channel for the vertical transistor and (ii) a second fin region providing a channel for an additional vertical transistor.

8 . The semiconductor structure of claim 7 , further comprising:

a third contact in the dummy fin region, the third contact extending from the first side of the vertical transistor to the second side of the vertical transistor; and

an additional interconnect structure connecting the third contact to a fourth contact, the fourth contact connecting to a source/drain region at a first side of the additional vertical transistor.

9 . The semiconductor structure of claim 7 , wherein the second contact connects to one or more back-end-of-line interconnects at the second side of the vertical transistor.

10 . The semiconductor structure of claim 7 , wherein the first contact is confined by one or more shallow trench isolation region structures.

11 . The semiconductor structure of claim 7 , further comprising an interlayer dielectric layer surrounding the first contact.

12 . The semiconductor structure of claim 11 , further comprising a third contact disposed in the interlayer dielectric layer connecting to a source/drain region at a first side of an additional vertical transistor, the third contact connecting to a power distribution network at the first side of the additional vertical transistor.

13 . An integrated circuit comprising:

a semiconductor structure comprising:

a first vertical transistor;

a second vertical transistor;

a first contact connecting to a source/drain region at a first side of the first vertical transistor;

a second contact extending from the first side of the first vertical transistor to a second side of the first vertical transistor;

a third contact connecting to a source/drain region at a first side of the second vertical transistor;

a fourth contact extending from the first side of the second vertical transistor to a second side of the second vertical transistor;

a first interconnect structure at the first side of the first vertical transistor connecting the first contact to the second contact; and

a second interconnect structure at the first side of the second vertical transistor connecting the third contact to the fourth contact;

wherein the second contact and the fourth contact are disposed in a region between the first vertical transistor and the second vertical transistor.

14 . The integrated circuit of claim 13 , wherein the second contact connects to one or more back-end-of-line interconnects at the second side of the first vertical transistor.

15 . The integrated circuit of claim 13 , wherein the second contact and the fourth contact are in a dummy fin region between (i) a first fin region providing a channel for the first vertical transistor and (ii) a second fin region providing a channel for the second vertical transistor.

16 . The integrated circuit of claim 13 , wherein the first contact is confined by one or more shallow trench isolation region structures.

17 . The integrated circuit of claim 13 , wherein the semiconductor structure further comprises an interlayer dielectric layer surrounding the first contact.

18 . The integrated circuit of claim 17 , wherein the semiconductor structure further comprises a fifth contact disposed in the interlayer dielectric layer connecting to a source/drain region at the first side of the second vertical transistor, the fifth contact connecting to a power distribution network at the first side of the second vertical transistor.