Triple layer high-k gate dielectric stack for workfunction engineering

1 . A method, comprising:

providing a structure having a first channel layer in an NMOS region and a second channel layer in a PMOS region;

depositing a first layer comprising hafnium oxide over both the first and the second channel layers;

forming a first dipole pattern over the second channel layer and not over the first channel layer, wherein the first dipole pattern includes a first metal;

annealing the structure such that the first metal is driven into the first layer under the first dipole pattern;

removing the first dipole pattern;

after removing the first dipole pattern, depositing a second layer comprising hafnium oxide over the first layer and over both the first and the second channel layers;

forming a second dipole pattern over the second layer and over the first channel layer and not over the second channel layer, wherein the second dipole pattern includes a second metal;

annealing the structure such that the second metal is driven into the second layer under the second dipole pattern;

removing the second dipole pattern; and

after removing the second dipole pattern, depositing a third layer comprising oxide over the second layer and over both the first and the second channel layers.

2 . The method of claim 1 , further comprising: depositing a work function metal layer over the third layer and over both the first and the second channel layers, the third layer comprising hafnium oxide.

3 . The method of claim 1 , wherein the forming of the first dipole pattern includes:

depositing a first dipole layer over both the first and the second channel layers, wherein the first dipole layer includes the first metal; and

patterning the first dipole layer into the first dipole pattern using photolithography and etching processes.

4 . The method of claim 1 , wherein the forming of the second dipole pattern includes:

depositing a second dipole layer over both the first and the second channel layers, wherein the second dipole layer includes the second metal; and

patterning the second dipole layer into the second dipole pattern using photolithography and etching processes.

5 . The method of claim 1 , wherein the first metal includes aluminum or niobium.

6 . The method of claim 1 , wherein the second metal includes lanthanum, yttrium, or strontium.

7 . The method of claim 1 , wherein each of the first, the second, and the third layers has a thickness in a range of about 2 Å to 15 Å.

8 . The method of claim 1 , wherein after the first metal is driven into the first layer, a concentration of the first metal in a portion of the first layer over the second channel layer is in a range of about 0.2% to about 30%.

9 . The method of claim 1 , wherein after the second metal is driven into the second layer, a concentration of the second metal in a portion of the second layer over the first channel layer is in a range of about 0.2% to about 30%.

10 . The method of claim 1 , wherein the first channel layer includes silicon and the second channel layer includes silicon or silicon germanium.

11 . A method of fabricating a semiconductor structure, the method comprising:

providing a first channel layer and a second channel layer;

depositing a first high-k dielectric layer over the first channel layer and over the second channel layer, wherein a first portion of the first high-k dielectric layer is disposed over the first channel layer and a second portion of the first high-k dielectric layer is disposed over the second channel layer;

driving a first dipole metal into the first portion of the first high-k dielectric layer to provide a first adjusted dielectric layer;

depositing a second high-k dielectric layer over the second portion of the first high-k dielectric layer and the first adjusted dielectric layer wherein a first portion of the second high-k dielectric layer is disposed over the first channel layer and a second portion of the second high-k dielectric layer is disposed over the second channel layer;

driving a second dipole metal into the second portion of the second high-k dielectric layer to provide a second adjusted dielectric layer; and

depositing a third high-k dielectric layer over the first portion of the second high-k dielectric layer and the second adjusted dielectric layer.

12 . The method of claim 11 , wherein the driving the first dipole metal includes annealing a first metal oxide layer comprising an oxide of the first dipole metal, the first metal oxide layer being disposed over the first portion of the first high-k dielectric layer during the annealing.

13 . The method of claim 12 , further comprising:

depositing the first metal oxide layer over the first portion of the first high-k dielectric layer and the second portion of the first high-k dielectric layer; and

removing the first metal oxide layer from over the second portion of the first high-k dielectric layer prior to the driving the annealing.

14 . The method of claim 11 , wherein the first dipole metal is one of aluminum (Al), niobium (Nb), and the second dipole metal is one of lanthanum (La), yttrium (Y), or strontium (Sr).

15 . The method of claim 11 , wherein each of the depositing the first high-k dielectric layer, the depositing the second high-k dielectric layer, and the depositing the third high-k dielectric layer include depositing hafnium oxide.

16 . A method, comprising:

providing a structure having a first channel layer in an NMOS region, and a second channel layer in a PMOS region;

depositing a first layer of a high-k dielectric material over both the first and the second channel layers;

forming a first metal oxide layer over the second channel layer and not over the first channel layer, wherein the first metal oxide layer includes a first metal;

annealing the structure such that the first metal is driven into the high-k dielectric material under the first metal oxide layer, and then removing the first metal oxide layer;

depositing a second layer of the high-k dielectric material over the first layer and over both the first and the second channel layers;

forming a second metal oxide layer over the second layer of the high-k dielectric material and over the first channel layer and not over the second channel layer, wherein the second metal oxide layer includes a second metal, the second metal different than the first metal;

annealing the structure such that the second metal is driven into the second layer of the high-k dielectric material under the second metal oxide layer, and then removing the second metal oxide layer; and

depositing a third layer of the high-k dielectric material over the second layer of the high-k dielectric material and over both the first and the second channel layers.

17 . The method of claim 16 , further comprising:

depositing an interfacial layer prior to depositing the first layer of the high-k dielectric material.

18 . The method of claim 16 , further comprising:

depositing a work function metal over the third layer of high-k dielectric material.

19 . The method of claim 16 , wherein the providing the structure includes providing a suspended nanostructure providing the first channel layer and a suspended nanostructure providing the second channel layer, wherein the suspended nanostructure is one of a nanowire, a nanobar, or a nanosheet.

20 . The method of claim 16 , wherein the annealing is controlled between 500° C. to about 1100° C.