Field effect transistor with gate electrode having multiple gate lengths
View Patent ↗An integrated circuit includes a semiconductor nanostructure transistor. The semiconductor nanostructure transistor includes a plurality of semiconductor nanostructures corresponding to channel regions conductor Nanostructure transistor. A gate metal surrounds the semiconductor nanostructures. The gate metal has differing gate length dimension above the semiconductor nanostructures compared to the gate length between the semiconductor nanostructures.
1 . A device, comprising:
a semiconductor substrate;
a first source/drain region of a transistor;
a second source/drain region of the transistor;
a plurality of stacked semiconductor nanostructures over the substrate and corresponding to channel regions of the transistor and each extending in a first direction between the first and second source/drain regions;
a plurality of first inner spacers each in contact with at least one of the semiconductor nanostructures and the first source/drain region, wherein a highest first inner spacer of the plurality of first inner spacers is on top of a highest semiconductor nanostructure of the plurality of semiconductor nanostructures and has a top surface that is higher than a top surface of the first source/drain region;
a plurality of second inner spacers each in contact with at least one of the semiconductor nanostructures and the second source/drain region, wherein a highest second inner spacer of the plurality of second inner spacers is on top of the highest semiconductor nanostructure;
a first gate spacer layer on a top surface of the highest first inner spacer;
a second gate spacer layer on a top surface of the highest second inner spacer;
a dielectric layer on the first source/drain region;
a source/drain contact extending through the dielectric layer to electrically couple to the first source/drain region, wherein the dielectric layer includes a first portion in contact with a sidewall of the first gate spacer layer between the first gate spacer layer and the source/drain contact, wherein the dielectric layer includes a second portion in contact with a sidewall of the highest first inner spacer between the highest first inner spacer and the first source/drain region; and
a gate metal including:
an upper portion above the semiconductor nanostructures and having a first width in the first direction; and
an interior portion between the semiconductor nanostructures and having a second width in the first direction larger than the first width, wherein the upper portion of the gate metal is positioned between the first and second gate spacer layers.
2 . The device of claim 1 , wherein a width of the first inner spacers in the first direction is less than a width of the first gate spacer layer in the first direction.
3 . The device of claim 2 , wherein the first inner spacers each have an outer sidewall in contact with the first source/drain region and substantially coplanar with an outer sidewall of the first gate spacer layer.
4 . The device of claim 3 , wherein each first inner spacer includes an interior sidewall laterally offset with respect to an interior sidewall of the first gate spacer layer.
5 . The device of claim 4 , wherein a width of the second inner spacers in the first direction is less than a width of the second gate spacer layer in the first direction.
6 . The device of claim 5 , wherein the second inner spacers each have an outer sidewall in contact with the second source/drain region and substantially coplanar with an outer sidewall of the second gate spacer layer.
7 . The device of claim 6 , wherein each second inner spacer includes an interior sidewall laterally offset with respect to an interior sidewall of the second gate spacer layer.
8 . The device of claim 5 , wherein the first and second inner spacers collectively bound the interior portion of the gate metal in the first direction.
9 . The device of claim 2 , wherein the first inner spacers each have a substantially same width.
10 . The device of claim 1 , wherein the gate metal includes an outer portion spaced apart from the semiconductor nanostructures in a second horizontal direction substantially perpendicular to the first horizontal direction and having a third width in the first direction less than the second width.
11 . The device of claim 10 , wherein the third width is equal to the first width.
12 . A method, comprising:
forming a plurality of stacked semiconductor nanostructures each extending in a first direction from a first source/drain region to a second source/drain region;
forming a gate spacer structure above the semiconductor nanostructures;
forming a plurality of inner spacers between the semiconductor nanostructures; and
forming a gate metal having an upper portion bounded in the first direction by the gate spacer structure and having a first width in the first direction, the gate metal having an interior portion between the semiconductor nanostructures bounded in the first direction by the inner spacers and having a second width in the first direction less than the first width;
forming a dielectric layer over the first source/drain region;
forming a source/drain contact extending through the dielectric layer to electrically couple to the first source/drain region, wherein a highest inner spacer of the plurality of inner spacers is in contact with the source/drain region and the dielectric layer and has a top surface that is higher than a top surface of the first source/drain region, wherein the dielectric layer includes a first portion in contact with a sidewall of the gate spacer structure between the gate spacer structure and the source/drain contact, wherein the dielectric layer includes a second portion in contact with a sidewall of the highest inner spacer between the highest inner spacer and the first source/drain region.
13 . The method of claim 12 , comprising:
forming, prior to forming the gate metal, a plurality of stacked sacrificial semiconductor nanostructures vertically interleaved with the stacked semiconductor nanostructures;
forming, prior to forming the gate metal, a sacrificial gate layer above the semiconductor nanostructures;
forming the gate spacer structure on sidewalls of the sacrificial gate layer; and
forming lateral recesses in the sacrificial semiconductor nanostructures with a third width in the first direction less than a width of the gate spacer structure.
14 . The method of claim 13 , comprising:
forming the inner spacers by depositing a dielectric material in the lateral recesses; and
aligning outer sidewalls of the semiconductor nanostructures and the inner spacers with outer sidewalls of the gate spacer structure.
15 . The method of claim 14 , comprising:
removing the sacrificial gate layer;
removing the sacrificial semiconductor nanostructures;
depositing the interior portion of the gate metal in place of the sacrificial semiconductor nanostructures; and
depositing the upper portion of the gate metal in place of the sacrificial gate layer.
16 . The method of claim 12 , wherein forming the gate metal includes forming an outer portion of the gate metal laterally adjacent to each of the semiconductor nanostructures in a second direction perpendicular to the first direction and having a third width less than the first width.
17 . The method of claim 16 , wherein the third width is equal to the second width.
18 . A method, comprising:
forming a plurality of stacked semiconductor nanostructures;
forming a plurality of stacked sacrificial semiconductor nanostructures vertically interleaved with the semiconductor nanostructures;
forming a sacrificial gate layer above the semiconductor nanostructures and having a first width in a first lateral direction;
forming first and second gate spacer layers on sidewalls of the sacrificial gate layer each having a second width in the first lateral direction;
forming recesses in the sacrificial semiconductor nanostructures in the first lateral direction with a third width in the first lateral direction less than the second width; and
forming a plurality of inner spacers in the recesses having the third width and each having an outer sidewall aligned with an outer sidewall of either the first gate spacer layer or the second gate spacer layer, wherein a highest inner spacer of the plurality of inner spacers is on top of a highest semiconductor nanostructure of the plurality of semiconductor nanostructures, wherein the first gate spacer layer is on a top surface of the highest inner spacer;
forming first and second source/drain regions, each of the semiconductor nanostructures extending in the first direction from the first source/drain region to the second source/drain region;
forming a dielectric layer over the first source/drain region; and
forming a source/drain contact extending through the dielectric layer to electrically couple to the first source/drain region, wherein the highest inner spacer is in contact with the first source/drain region and the dielectric layer and has a top surface that is higher than a top surface of the first source/drain region, wherein the dielectric layer includes a first portion in contact with a sidewall of the first gate spacer layer between the first gate spacer layer and the source/drain contact, wherein the dielectric layer includes a second portion in contact with a sidewall of the highest inner spacer between the highest inner spacer and the first source/drain region.
19 . The method of claim 18 , comprising:
removing the sacrificial gate layer;
removing the sacrificial semiconductor layers;
forming an interior portion of a gate electrode between the semiconductor nanostructures in place of the sacrificial semiconductor nanostructures and bounded in the first direction by the inner spacers; and
forming an upper portion of the gate electrode in place of the sacrificial gate layer.
20 . The method of claim 19 , comprising forming an outer portion of the gate electrode laterally adjacent to each of the semiconductor nanostructures in a second direction perpendicular to the first direction and being bounded in the first direction between the first and second gate spacer layers.