Low resistance metal to semiconductor contacts for integrated NMOS and PMOS transistors
Complementary metal-oxide-semiconductor (CMOS) devices and methods related to selective metal contacts to n-type and p-type source and drain semiconductors are discussed. A p-type metal is deposited on n- and p-type source/drains. The p-type metal is selectively removed from the n-type source/drains but remains on dielectric materials adjacent the n-type source/drains. An n-type metal is deposited on the n-type source/drains while the remaining p-type metal seals the dielectric materials to protect the n-type metal from contamination. The n-type metal is then sealed using another p-type metal. A contact fill material contacts the resultant source and drain contact stacks.
1 . An apparatus, comprising:
a first transistor comprising:
a first source or drain region comprising an n-type semiconductor material;
a dielectric material comprising a sidewall adjacent the first source or drain region;
a first metal layer comprising a first p-type metal on the sidewall;
a second metal layer comprising an n-type metal, wherein the second metal layer has a first portion discontinuous from a second portion, wherein the first portion is on a top surface of the first source or drain region and the second portion is on the first metal layer;
a third metal layer comprising a second p-type metal or the first p-type metal on the second metal layer; and
a first metal fill of a first metal on the third metal layer, and in a region laterally adjacent the sidewall; and
a second transistor comprising:
a second source or drain region comprising a p-type semiconductor material;
a fourth metal layer comprising the first p-type metal on a top surface of the second source or drain region; and
a second metal fill of the first metal on the fourth metal layer.
2 . The apparatus of claim 1 , wherein the n-type metal comprises at least one of cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium.
3 . The apparatus of claim 1 , wherein the n-type metal comprises at least one of magnesium, calcium, strontium, or barium.
4 . The apparatus of claim 1 , wherein the n-type metal comprises at least one of scandium, yttrium, lanthanum, titanium, zirconium, or hafnium.
5 . The apparatus of claim 1 , wherein the third metal layer comprises the first p-type metal, and the first p-type metal comprises one of tungsten, molybdenum, manganese, cobalt, nickel, ruthenium, rhenium, osmium, iridium, platinum, rhodium, or palladium.
6 . The apparatus of claim 1 , wherein the third metal layer comprises the second p-type metal, the first p-type metal comprises one of tungsten, molybdenum, manganese, cobalt, nickel, ruthenium, rhenium, osmium, iridium, platinum, rhodium, or palladium, and the second p-type metal comprises another of tungsten, molybdenum, manganese, cobalt, nickel, ruthenium, rhenium, osmium, iridium, platinum, rhodium, or palladium.
7 . The apparatus of claim 1 , wherein a portion of the third metal layer is between the first metal layer and the first metal fill, the third metal layer comprising the second p-type metal.
8 . The apparatus of claim 1 , wherein the first metal comprises tungsten.
9 . The apparatus of claim 1 , wherein the n-type semiconductor material comprises silicon and/or germanium doped with one or more of phosphorous, arsenic, antimony, and bismuth.
10 . The apparatus of claim 1 , wherein the p-type semiconductor material comprises silicon and/or germanium doped with one or more of boron, gallium, or indium.
11 . The apparatus of claim 1 , further comprising:
an integrated circuit die comprising the first transistor and the second transistor; and
a power supply coupled to the integrated circuit die.
12 . An apparatus, comprising:
a first transistor comprising:
an n-type semiconductor material source or drain;
a dielectric material comprising a sidewall adjacent the n-type semiconductor material source or drain;
a first p-type metal on the sidewall;
an n-type metal, wherein the n-type metal has a first portion discontinuous from a second portion, wherein the first portion is on a top surface of the n-type semiconductor material source or drain and the second portion is on the first p-type metal;
a second p-type metal on the n-type metal; and
a metal fill on the second p-type metal, and in a region laterally adjacent the sidewall; and
a second transistor comprising:
a p-type semiconductor material source or drain;
the first p-type metal on a top surface of the p-type semiconductor material source or drain; and
the metal fill on the first p-type metal.
13 . The apparatus of claim 12 , wherein the n-type metal comprises at least one of cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium.
14 . The apparatus of claim 12 , wherein the n-type metal comprises at least one of magnesium, calcium, strontium, or barium.
15 . The apparatus of claim 12 , wherein the n-type metal comprises at least one of scandium, yttrium, lanthanum, titanium, zirconium, or hafnium.
16 . The apparatus of claim 12 , wherein the first p-type metal comprises one of tungsten, molybdenum, manganese, cobalt, nickel, ruthenium, rhenium, osmium, iridium, platinum, rhodium, or palladium, and the second p-type metal comprises another of tungsten, molybdenum, manganese, cobalt, nickel, ruthenium, rhenium, osmium, iridium, platinum, rhodium, or palladium.
17 . The apparatus of claim 12 , wherein the n-type semiconductor material source or drain is adjacent a channel region, the channel region comprising a portion of a semiconductor fin.
18 . The apparatus of claim 12 , wherein the metal fill comprises tungsten.
19 . The apparatus of claim 12 , wherein the n-type semiconductor material source or drain comprises silicon and/or germanium doped with one or more of phosphorous, arsenic, antimony, and bismuth.
20 . The apparatus of claim 12 , wherein the p-type semiconductor material source or drain comprises silicon and/or germanium doped with one or more of boron, gallium, or indium.
21 . The apparatus of claim 12 , further comprising:
an integrated circuit die comprising the first transistor and the second transistor; and
a power supply coupled to the integrated circuit die.