Large dimension metal gate field-effect transistor (FET) with metal gate dummy structures
In accordance with some aspects of the disclosure, a semiconductor structure is provided. The semiconductor structure includes: an active region; and a gate stack disposed on the active region. The gate stack includes: at least one gate dielectric layer disposed on the active region; and a metal gate structure disposed on the at least one gate dielectric layer. The metal gate structure includes: a metal gate layer comprising a first material; and at least one dummy structure disposed in the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material. The second material is different from the first material.
1 . A semiconductor structure comprising:
an active region; and
a gate stack disposed on the active region, the gate stack comprising:
at least one gate dielectric layer disposed on the active region; and
a metal gate structure disposed on the at least one gate dielectric layer, the metal gate structure comprising:
a metal gate layer comprising a first material; and
at least one dummy structure surrounded by the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material, wherein the second material is different from the first material.
2 . The semiconductor structure of claim 1 , wherein the metal gate structure is of a first semiconductor conductivity type.
3 . The semiconductor structure of claim 1 , wherein the metal gate structure is of a second semiconductor conductivity type.
4 . The semiconductor structure of claim 1 , wherein the metal gate structure comprises a plurality of the dummy structures, the plurality of the dummy structures forming a dummy pattern.
5 . The semiconductor structure of claim 4 , wherein the dummy structures are arranged in rows and columns in a horizontal plane.
6 . The semiconductor structure of claim 1 , wherein the first material is a first metal.
7 . The semiconductor structure of claim 6 , wherein the second material is a second metal, wherein the second metal is different from the first metal.
8 . The semiconductor structure of claim 1 , wherein the second material is polysilicon.
9 . The semiconductor structure of claim 1 , wherein the second material is silicon oxide.
10 . The semiconductor structure of claim 1 , wherein the second material is silicon nitride or a dielectric material.
11 . The semiconductor structure of claim 1 , wherein the metal gate structure has a uniform gate thickness.
12 . The semiconductor structure of claim 1 , further comprising two sidewall spacers respectively disposed on two sidewalls of the gate stack.
13 . A method comprising:
forming an active region; and
forming a gate stack on the active region, the gate stack comprising:
at least one gate dielectric layer disposed on the active region; and
a metal gate structure disposed on the at least one gate dielectric layer, the metal gate structure comprising:
a metal gate layer comprising a first material; and
at least one dummy structure surrounded by the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material, wherein the second material is different from the first material.
14 . The method of claim 13 , wherein the metal gate structure is of a first semiconductor conductivity type.
15 . The method of claim 13 , wherein the metal gate structure is of a second semiconductor conductivity type.
16 . The method of claim 13 , wherein the metal gate structure comprises a plurality of the dummy structures, the plurality of the dummy structures forming a dummy pattern.
17 . The method of claim 16 , wherein the dummy structures are arranged in rows and columns in a horizontal plane.
18 . A field-effect transistor (FET) comprising:
a semiconductor substrate having an active region, the active region including a source region and a drain region separated by a channel region; and
a gate stack disposed over the channel region, the gate stack comprising:
at least one gate dielectric layer disposed on the active region; and
a metal gate structure disposed on the at least one gate dielectric layer, the metal gate structure comprising:
a metal gate layer comprising a first material; and
a plurality of dummy structures surrounded by the metal gate layer, the plurality of dummy structures forming a dummy pattern and extending vertically through an entire thickness of the metal gate electrode, wherein the dummy structures comprise a second material that is different from the first material.
19 . The FET of claim 18 , wherein the FET is a p-type metal-oxide-semiconductor (PMOS) device.
20 . The FET of claim 18 , wherein the FET is an n-type metal-oxide-semiconductor (NMOS) device.