Semiconductor device including an internal spacer

1 . A semiconductor device comprising:

a substrate including a first region, a second region, and a third region;

a first nanowire and a second nanowire, which are sequentially spaced apart from each other and stacked on the first region of the substrate, the first nanowire and the second nanowire each extending in a first direction;

a third nanowire and a fourth nanowire, which are sequentially spaced apart from each other and stacked on the second region of the substrate, the third nanowire and the fourth nanowire each extending in the first direction;

a fifth nanowire and a sixth nanowire, which are sequentially spaced apart from each other and stacked on the third region of the substrate, the fifth nanowire and the sixth nanowire each extending in the first direction;

a first gate electrode surrounding the first nanowire and the second nanowire, the first gate electrode extending in a second direction different from the first direction;

a second gate electrode surrounding the third nanowire and the fourth nanowire, the second gate electrode extending in the second direction;

a third gate electrode surrounding the fifth nanowire and the sixth nanowire, the third gate electrode extending in the second direction;

a first interface layer between the first gate electrode and the second nanowire, the first interface layer having a first thickness, the first interface layer being in contact with each of an upper face and a bottom face of the second nanowire;

a second interface layer between the third gate electrode and the sixth nanowire, the second interface layer having a second thickness greater than the first thickness, the second interface layer being in contact with each of an upper face and a bottom face of the sixth nanowire; and

a first internal spacer on a side wall of at least one of the first gate electrode, the second gate electrode, and the third gate electrode,

wherein a first length of the first nanowire in the first direction is smaller than a second length of the third nanowire in the first direction,

wherein a thickness of a top region of the first gate electrode over the second nanowire is thicker than an intermediate region of the first gate electrode between the first nanowire and the second nanowire, and

wherein the first internal spacer is on one sidewall selected from the sidewall of the first gate electrode, the sidewall of the second gate electrode, and the sidewall of the third gate electrode, provided that the first internal spacer is not on two different sidewalls selected from the sidewall of the first gate electrode, the sidewall of the second gate electrode, and the sidewall of the third gate electrode, or

the first internal spacer is on two sidewalls selected from the sidewall of the first gate electrode, the sidewall of the second gate electrode, and the sidewall of the third gate electrode, provided that the first internal spacer is not on one different sidewall selected from the sidewall of the first gate electrode, the sidewall of the second gate electrode, and the sidewall of the third gate electrode.

2 . The semiconductor device of claim 1 , wherein

each of the first region, the second region, and the third region of the substrate is an NMOS region, or

each of the first region, the second region, and the third region of the substrate is a PMOS region.

3 . The semiconductor device of claim 2 , further comprising:

a seventh nanowire, an eighth nanowire, a ninth nanowire, a tenth nanowire, an eleventh nanowire, and a twelfth nanowire each extending in the first direction;

a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode each extending in the second direction;

a third interface layer between the fourth gate electrode and the eighth nanowire, the third interface layer having a third thickness;

a fourth interface layer between the sixth gate electrode and the twelfth nanowire, the fourth interface layer having a fourth thickness greater than the third thickness; and

a second internal spacer on side walls of at least one of the fourth gate electrode, the fifth gate electrode, and the sixth gate electrode, wherein the substrate further includes a fourth region, a fifth region, and a sixth region as the PMOS region,

the seventh nanowire and the eighth nanowire are sequentially spaced apart from each other and stacked on the fourth region of the substrate,

the ninth nanowire and the tenth nanowire are sequentially spaced apart from each other and stacked on the fifth region of the substrate,

the eleventh nanowire and the twelfth nanowire are sequentially separated from each other and stacked on the sixth region of the substrate,

the fourth gate electrode surrounds the seventh nanowire and the eighth nanowire,

the fifth gate electrode surrounds the ninth nanowire and the tenth nanowire,

the sixth gate electrode surrounds the eleventh nanowire and the twelfth nanowire, and

a length of the seventh nanowire in the first direction is smaller than a length of the ninth nanowire in the first direction.

4 . The semiconductor device of claim 1 , further comprising:

a third interface layer between the second gate electrode and the fourth nanowire, wherein

a thickness of the third interface layer smaller than the second thickness of the second interface layer.

5 . The semiconductor device of claim 4 , wherein the first thickness of the first interface layer is same as the thickness of the third interface layer.

6 . The semiconductor device of claim 1 , further comprising:

a first gate insulation layer between the first gate electrode and the first interface layer; and

a second gate insulation layer between the third gate electrode and the second interface layer.

7 . The semiconductor device of claim 1 , wherein a third length of the fifth nanowire in the first direction is smaller than the second length of the third nanowire in the first direction.

8 . The semiconductor device of claim 7 , wherein the third length of the fifth nanowire in the first direction is same as the first length of the first nanowire in the first direction.

9 . The semiconductor device of claim 1 , wherein

the first thickness of the first interface layer is 0.2 nm to 2.0 nm, and

the second thickness of the second interface layer is 2.5 nm to 4.5 nm.

10 . The semiconductor device of claim 1 , wherein

the first length of the first nanowire in the first direction is 5 nm to 20 nm, and

the second length of the third nanowire in the first direction is 30 nm to 300 nm.

11 . A semiconductor device comprising:

a substrate including a first region, a second region, and a third region that are NMOS regions;

a first plurality of nanowires on the first region of the substrate, each extending in a first direction;

a second plurality of nanowires on the second region of the substrate, each extending in the first direction;

a third plurality of nanowires on the third region of the substrate, each extending in the first direction;

a first gate electrode surrounding the first plurality of nanowires and extending in a second direction different from the first direction;

a second gate electrode surrounding the second plurality of nanowires and extending in the second direction;

a third gate electrode surrounding the third plurality of nanowires and extending in the second direction;

a first interface layer between the first gate electrode and the first plurality of nanowires, the first interface layer having a first thickness, the first interface layer being in contact with each of an upper face and a bottom face of the first plurality of nanowires;

a second interface layer between the third gate electrode and the third plurality of nanowires, the second interface layer having a second thickness greater than the first thickness, the second interface layer being in contact with each of an upper face and a bottom face of the third plurality of nanowires;

a first gate insulation layer between the first gate electrode and the first interface layer;

a second gate insulation layer between the third gate electrode and the second interface layer; and

a first internal spacer on a side wall of at least one of the first gate electrode, the second gate electrode, and the third gate electrode,

a first length of the first plurality of nanowires in the first direction being smaller than a second length of the second plurality of nanowires in the first direction,

wherein a thickness of a top region of the first gate electrode over the first plurality of nanowires is thicker than regions of the first gate electrode respectively between the first plurality of nanowires, and

wherein the first internal spacer is on one sidewall selected from the sidewall of the first gate electrode, the sidewall of the second gate electrode, and the sidewall of the third gate electrode, provided that the first internal spacer is not on two different sidewalls selected from the sidewall of the first gate electrode, the sidewall of the second gate electrode, and the sidewall of the third gate electrode, or

the first internal spacer is on two sidewalls selected from the sidewall of the first gate electrode, the sidewall of the second gate electrode, and the sidewall of the third gate electrode, provided that the first internal spacer is not on one different sidewall selected from the sidewall of the first gate electrode, the sidewall of the second gate electrode, and the sidewall of the third gate electrode.

12 . The semiconductor device of claim 11 , further comprising:

a fourth plurality of nanowires on a fourth region of the substrate and extending in the first direction;

a fifth plurality of nanowires on a fifth region of the substrate and extending in the first direction;

a sixth plurality of nanowires on a sixth region of the substrate and extending in the first direction;

a fourth gate electrode surrounding the fourth plurality of nanowires and extending in the second direction;

a fifth gate electrode surrounding the fifth plurality of nanowires and extending in the second direction;

a sixth gate electrode surrounding the sixth plurality of nanowires and extending in the second direction;

a third interface layer between the fourth gate electrode and the fourth plurality of nanowires, the third interface layer having a third thickness;

a fourth interface layer between the sixth gate electrode and the sixth plurality of nanowires, the fourth interface layer having a fourth thickness greater than the third thickness;

a third gate insulation layer between the fourth gate electrode and the third interface layer;

a fourth gate insulation layer between the sixth gate electrode and the fourth interface layer; and

a second internal spacer at least one of between the fourth plurality of nanowires, between the fifth plurality of nanowires, and between the sixth plurality of nanowires, wherein

the fourth region, the fifth region, and the sixth region each are a PMOS region in the substrate, and

a length of the fourth plurality of nanowires in the first direction is smaller than a length of the fifth plurality of nanowires in the first direction.

13 . The semiconductor device of claim 11 , further comprising:

a third interface layer between the second gate electrode and the second plurality of nanowires, wherein

a thickness of the third interface layer is smaller than the second thickness of the second interface layer.

14 . The semiconductor device of claim 11 , wherein a third length of the third plurality of nanowires in the first direction is smaller than the second length of the second plurality of nanowires in the first direction.

15 . The semiconductor device of claim 11 , wherein a width of the first gate electrode in the first direction is smaller than a width of the second gate electrode in the first direction.