Method of manufacturing a semiconductor device having a dumbbell-shaped contact connecting differently recessed source/drain epitaxial layers
In a method of manufacturing a semiconductor device, an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer respectively formed, a dielectric layer is formed over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, a first opening is formed in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening is formed in the dielectric layer to expose a part of the p-type source/drain epitaxial layer, and the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer respectively recessed. A recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.
1 . A method of manufacturing a semiconductor device, comprising:
forming an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer, respectively;
forming a dielectric layer over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer;
forming a first opening in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening in the dielectric layer to expose a part of the p-type source/drain epitaxial layer;
recessing the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, respectively; and
forming at least one elongate source/drain contact spanning and connecting two or more source/drain epitaxial layers, the at least one elongate source/drain contact having a dumbbell shape in a plan view with end portions having a greater width than a center portion located between the end portions,
wherein a recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.
2 . The method of claim 1 , wherein the recessing amount of the n-type source/drain epitaxial layer is greater than the recessing amount of the p-type source/drain epitaxial layer.
3 . The method of claim 2 , wherein a difference between the recessing amount of the n-type source/drain epitaxial layer and the recessing amount of the p-type source/drain epitaxial layer is more than 1 nm.
4 . The method of claim 2 , wherein the recessing amount of the n-type source/drain epitaxial layer is in a range from 11 nm to 18 nm.
5 . The method of claim 2 , wherein the recessing amount of the p-type source/drain epitaxial layer is in a range from 7 nm to 12 nm.
6 . The method of claim 2 , wherein:
the n-type source/drain epitaxial layer includes a SiP layer, and the p-type source/drain epitaxial layer includes a SiGe layer, and
the recessing the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer comprises plasma etching using a gas containing sulfur.
7 . The method of claim 6 , wherein the gas containing sulfur is at least one of COS or SF 6 .
8 . The method of claim 1 , wherein the first opening is discontinuous from the second opening.
9 . The method of claim 1 , wherein the first opening and the second opening form a continuous opening.
10 . The method of claim 1 , wherein the end portions of the at least one elongate source/drain contact have a width 0.5 nm to 2 nm greater than a width of the center portion.
11 . A method of manufacturing a semiconductor device, comprising:
forming an n-type source/drain epitaxial layer over one or more first fin structures and a p-type source/drain epitaxial layer over one or more second fin structures;
forming a dielectric layer over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer;
forming a first opening in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening in the dielectric layer to expose a part of the p-type source/drain epitaxial layer;
recessing the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, respectively; and
forming a first source/drain contact over the recessed n-type source/drain epitaxial layer, and a second source/drain contact over the recessed p-type source/drain epitaxial layer,
wherein after the recessing, a top of the n-type source/drain epitaxial layer is lower than a top of the p-type source/drain epitaxial layer,
wherein at least one of the first source/drain contact and the second source/drain contact is a dual hammer head shape in a plan view, the dual hammer head shape having end portions that are wider than a center portion between the end portions, and is disposed over and connects two or more source/drain epitaxial layers.
12 . The method of claim 11 , further comprising forming a first silicide layer on the recessed n-type source/drain epitaxial layer and a second silicide layer on the recessed p-type source/drain epitaxial layer, before the first and second source/drain contacts are formed.
13 . The method of claim 12 , wherein:
the n-type source/drain epitaxial layer includes a SiP layer, and the p-type source/drain epitaxial layer includes a SiGe layer, and
the recessing the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer comprises plasma etching at the same time using a gas containing sulfur.
14 . The method of claim 13 , wherein the gas containing sulfur is at least one of COS or SF 6 .
15 . The method of claim 11 , wherein a difference between a recessing amount of the n-type source/drain epitaxial layer and a recessing amount of the p-type source/drain epitaxial layer is in a range from 2 nm to 6 nm.
16 . The method of claim 11 , wherein a recessing amount of the n-type source/drain epitaxial layer is in a range from 12 nm to 15 nm.
17 . The method of claim 11 , wherein a recessing amount of the p-type source/drain epitaxial layer is in a range from 8 nm to 10 nm.
18 . The method of claim 11 , further comprising, before the recessing the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer:
forming an insulating liner layer on an inner sidewall of the first and second openings and on the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, respectively; and
removing a part of the insulating liner layer formed on the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer.
19 . A method of manufacturing a semiconductor device, comprising:
forming an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer;
forming a dielectric layer over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer;
forming an opening in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a part of the p-type source/drain epitaxial layer;
recessing the n-type source/drain epitaxial layer;
recessing the p-type source/drain epitaxial layer; and
forming a source/drain contact over the recessed n-type source/drain epitaxial layer and the recessed p-type source/drain epitaxial layer,
wherein a recessing amount of the n-type source/drain epitaxial layer is greater than a recessing amount of the p-type source/drain epitaxial layer,
wherein a length of the source/drain contact is more than 50 nm, and
wherein the source/drain contact has a dumbbell shape in plan view.
20 . The method of claim 19 , wherein:
the n-type source/drain epitaxial layer includes a SiP layer, and the p-type source/drain epitaxial layer includes a SiGe layer, and
the recessing the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer occur at a same time by plasma etching using an etching source gas including at least one gas of COS or SF 6 , and one or more gases of fluorocarbon, H 2 , O 2 , Ar or N 2 .