Semiconductor device including isolation pattern formed based on insulating layer and method for manufacturing the same
A method for manufacturing a semiconductor device includes: forming a semiconductor structure and a dummy structure on a substrate; forming a first insulating layer between the semiconductor structure and the dummy structure; forming a first space by removing the dummy structure; forming an isolation pattern in the first space; forming a main gate sacrificial pattern crossing the first direction to overlap the semiconductor structure; forming second spaces by removing portions of the semiconductor structure at both sides of the main gate sacrificial pattern, and forming source/drain patterns in the second spaces; forming a second insulating layer on the source/drain patterns; forming a third space by removing the main gate sacrificial pattern, and forming a gate electrode in the third space; and forming fourth spaces by removing the second insulating layer, and forming, in the fourth spaces, contact structures connected to the source/drain patterns and disposed on both sides of the isolation pattern.
1 . A method for manufacturing a semiconductor device, the method comprising:
forming semiconductor structures and a dummy structure extending in a first direction on a substrate;
forming a first insulating layer between the semiconductor structures and the dummy structure;
forming a first space in the first insulating layer by removing the dummy structure;
forming an isolation pattern in the first space in the first insulating layer;
forming a main gate sacrificial pattern extending in a second direction crossing the first direction to overlap the semiconductor structures;
forming second spaces by removing portions of the semiconductor structures at both sides of the main gate sacrificial pattern, and forming source/drain patterns in the second spaces;
forming a second insulating layer on the source/drain patterns;
forming a third space by removing the main gate sacrificial pattern, and forming a gate electrode in the third space; and
forming fourth spaces by removing the second insulating layer, and forming, in the fourth spaces, contact structures connected to the source/drain patterns and disposed on both sides of the isolation pattern.
2 . The method of claim 1 , wherein the isolation pattern includes a silicon oxide or a low-k dielectric material.
3 . The method of claim 1 , further comprising removing the first insulating layer against the isolation pattern prior to the forming the source/drain patterns,
wherein a material forming the first insulating layer has a higher etch rate than a material forming the isolation pattern.
4 . The method of claim 1 , wherein an upper surface of the isolation pattern is at a level higher than upper surfaces of the semiconductor structures.
5 . The method of claim 1 , wherein an upper surface of the isolation pattern is at a level higher than an upper surface of the gate electrode.
6 . The method of claim 1 , wherein the semiconductor structures and the dummy structure comprise a same material.
7 . The method of claim 6 , wherein the forming the semiconductor structures and the dummy structure comprises:
alternately stacking a first material layer and a second material layer on the substrate;
forming a hard mask pattern on the stacked first material layer and second material layer; and
forming the semiconductor structures and the dummy structure by patterning the first material layer and the second material layer based on the hard mask pattern.
8 . The method of claim 7 , wherein the first material layer comprises silicon germanium, and the second material layer comprises silicon.
9 . The method of claim 7 , wherein each of the semiconductor structures comprises a plurality of sub-gate sacrificial patterns and a plurality of semiconductor patterns, and
wherein the dummy structure comprises a plurality of dummy gate sacrificial patterns and a plurality of dummy semiconductor patterns.
10 . The method of claim 1 , further comprising, after the forming the isolation pattern, removing the first insulating layer.
11 . The method of claim 1 , wherein the forming the first space comprises:
forming a first photoresist pattern on the semiconductor structures among the semiconductor structures and the dummy structure; and
removing the dummy structure by performing an etching process based on the first photoresist pattern.
12 . The method of claim 11 , wherein the first photoresist pattern is formed on a portion of the first insulating layer disposed adjacent to the semiconductor structures without being formed on a portion of the first insulating layer disposed adjacent to the dummy structure, and the first insulating layer is not removed in the etching process.
13 . The method of claim 1 , wherein the forming the contact structures comprises:
forming a second photoresist pattern on the second insulating layer such that an opening overlapping the isolation pattern and the source/drain patterns is obtained;
removing the second insulating layer based on the second photoresist pattern to form the fourth spaces; and
forming the contact structures by depositing a conductive material in the fourth spaces and performing a chemical mechanical polishing process.
14 . The method of claim 1 , wherein the isolation pattern is surrounded by the second insulating layer in plan view.