Logic gates

1 . A logic gate, comprising:

a semiconductor material;

a plurality of first source/drain regions disposed in the semiconductor material, each first source/drain region of the plurality of first source/drain regions having a first width;

a second source/drain region disposed in the semiconductor material, the second source/drain region having a second width that is different than the first width;

a plurality of transistor gates disposed on the semiconductor material; and

a plurality of electrical contacts coupled to the plurality of first source/drain regions and the second source/drain region, wherein:

each respective electrical contact of the plurality of electrical contacts that are coupled to each respective first source/drain region of the plurality of first source/drain regions is located off-center in each respective first source/drain region and an electrical contact of the plurality of electrical contacts that is coupled to the second source/drain region is located in a center of the second source/drain region.

2 . The logic gate of claim 1 , wherein the logic gate further comprises a NAND gate or a NOR gate.

3 . The logic gate of claim 1 , wherein the first width is at least two times greater than the second width.

4 . The logic gate of claim 1 , wherein the second width is at least three times greater than the first width.

5 . The logic gate of claim 4 , wherein the second width is three times greater than the first width.

6 . A logic gate, comprising:

a semiconductor material;

a plurality of first source/drain regions disposed in the semiconductor material, each first source/drain region of the plurality of first source/drain regions having a first width;

a second source/drain region disposed in the semiconductor material, the second source/drain region having a second width that is different than the first width;

a plurality of transistor gates disposed on the semiconductor material, wherein each transistor gate of the plurality of transistor gates is respectively disposed between a first source/drain region of the plurality of first source/drain regions and the second source/drain region; and

a plurality of local interface contacts (LICON), wherein:

a respective LICON of the plurality of LICON is coupled to each first source/drain region of the plurality of first source/drain regions;

a respective LICON of the plurality of LICON is coupled to the second source/drain region; and

the respective LICON of the plurality of LICON that are coupled to each first source/drain region of the plurality of first source/drain regions is located off-center in each first source/drain region when the first width is greater than the second width, and the respective LICON of the plurality of LICON that are coupled to the second source/drain region are located in a center of the second source/drain region.

7 . The logic gate of claim 6 , wherein the plurality of first source/drain regions and the second source/drain region are n-doped regions.

8 . The logic gate of claim 6 , wherein the plurality of first source/drain regions and the second source/drain region are p-doped regions.

9 . The logic gate of claim 8 , further comprising a liner material overlying the plurality of first source/drain regions, the second source/drain region, and the plurality of transistor gates, the liner material including a first portion of the liner material having a third width and a second portion of the liner material having a fourth width that is different than the third width.

10 . The logic gate of claim 6 , wherein:

the first width is at least two times greater than the second width; or

the second width is at least three times greater than the first width.

11 . A logic gate, comprising:

a semiconductor material;

first source/drain regions disposed in the semiconductor material, wherein each of the first source/drain regions has a first width;

a second source/drain region disposed in the semiconductor material, wherein the second source/drain region has a second width that is different than the first width;

transistor gates disposed on the semiconductor material, wherein the transistor gates have a non-uniform pitch; and

local interface contacts (LICON) coupled to each of the first source/drain regions and the second source/drain region, wherein each respective LICON that is coupled to each first source/drain region is located off-center in each first source/drain region when the first width is greater than the second width, and each respective LICON that is coupled to the second source/drain region is located in a center of the second source/drain region.

12 . The logic gate of claim 11 , wherein the logic gate is dummy gate-free and active region-free.

13 . The logic gate of claim 11 , wherein:

the logic gate is a NAND gate, and wherein a first subset of the transistor gates has a pitch that is at least two times a pitch of a second subset of the transistor gates; or

the logic gate is a NOR gate, and wherein the first subset of the transistor gates has a pitch that is at least three times a pitch of the second subset of the transistor gates.

14 . The logic gate of claim 11 , wherein the first source/drain regions and the second source/drain regions are formed of epitaxially grown silicon-germanium.