Semiconductor device and fabricating method of the same
A semiconductor device includes a substrate. A high voltage transistor is disposed within a high voltage region of the substrate. The high voltage transistor includes a first gate dielectric layer disposed on the substrate. A first gate electrode is disposed on the first gate dielectric layer. A first source/drain doping region and a second source/drain doping region are respectively disposed in the substrate at two sides of the first gate electrode. A first silicide layer covers and contacts the first source/drain doping region and a second silicide layer covers and contacts the second source/drain doping region. A first conductive plate penetrates the first silicide layer and contacts the first source/drain doping region. A second conductive plate penetrates the second silicide layer and contacts the second source/drain doping region.
1 . A semiconductor device, comprising:
a substrate comprising a high voltage region and a low voltage region;
a first deep trench isolation and a second deep trench isolation embedded in the substrate within the high voltage region;
a high voltage transistor disposed within the high voltage region, wherein the high voltage transistor comprises:
a first gate dielectric layer disposed on a first surface of the substrate, wherein the first gate dielectric layer is between a first part of the first deep trench isolation and a first part of the second deep trench isolation, the first gate dielectric layer contacts the first deep trench isolation and the second deep trench isolation, and a top surface of the first gate dielectric layer is aligned with a top surface of the first deep trench isolation and a top surface of the second deep trench isolation;
a first gate electrode disposed on the first gate dielectric layer;
a first source/drain doping region disposed within the substrate, wherein a second part of the first deep trench isolation defines an outer edge of the first source/drain doping region, the first part of the first deep trench isolation is embedded within the first source/drain doping region, and a bottom of the first part of the first deep trench isolation is aligned with a bottom of the second part of the first deep trench isolation;
a second source/drain doping region disposed within the substrate, wherein a second part of the second deep trench isolation defines an outer edge of the second source/drain doping region, the first part of second deep trench isolation is embedded within the second source/drain doping region, and a bottom of the first part of the second deep trench isolation is aligned with a bottom of the second part of the second deep trench isolation;
a first silicide layer covering and contacting the first source/drain doping region; and
a second silicide layer covering and contacting the second source/drain doping region;
a first conductive plate penetrating the first silicide layer and contacting the first source/drain doping region, wherein as seen from a top view, only the first conductive plate penetrates the first silicide layer on the first source/drain doping region, and no other conductive elements penetrate the first silicide layer; and
a second conductive plate penetrating the second silicide layer and contacting the second source/drain doping region;
a fin transistor disposed within the low voltage region, wherein the fin transistor comprises:
a fin structure protruding from a second surface of the substrate;
a second gate electrode disposed on the fin structure; and
two shallow trench isolations disposed at two sides of the fin structure.
2 . The semiconductor device of claim 1 , wherein a first direction is parallel with a long side of the first gate electrode, a second direction is parallel with a short side of the first gate electrode, a third direction is parallel with the short side of the first gate electrode and the third direction is in a reverse direction of the second direction.
3 . The semiconductor device of claim 2 , wherein along the first direction, a shortest distance between the first conductive plate and an edge of the first silicide layer is between 10 and 90 nanometers.
4 . The semiconductor device of claim 2 , wherein along the second direction, a shortest distance between the first conductive plate and an edge of the first silicide layer is between 10 and 90 nanometers.
5 . The semiconductor device of claim 2 , wherein along the third direction, a shortest distance between the first conductive plate and the first gate electrode is between 350 and 1050 nanometers.
6 . The semiconductor device of claim 1 , wherein a depth of each of the two shallow trench isolations is smaller than a depth of the first deep trench isolation.
7 . The semiconductor device of claim 1 , wherein there is no epitaxial layer on the first source/drain doping region and the second source/drain doping region.
8 . The semiconductor device of claim 1 , wherein a voltage of the high voltage transistor is 40 volts.
9 . The semiconductor device of claim 1 , further comprising a first epitaxial layer and a second epitaxial layer respectively embedded within the fin structure at two sides of the second gate electrode.
10 . A fabricating method of a semiconductor device, comprising:
providing a substrate comprising a high voltage region and a low voltage region;
forming a first deep trench isolation and a second deep trench isolation embedded in the substrate within the high voltage region;
forming a high voltage transistor disposed within the high voltage region, wherein the high voltage transistor comprises
a first gate dielectric layer disposed on a first surface of the substrate, wherein the first gate dielectric layer is between a first part of the first deep trench isolation and a first part of the second deep trench isolation, the first gate dielectric layer contacts the first deep trench isolation and the second deep trench isolation, and a top surface of the first gate dielectric layer is aligned with a top surface of the first deep trench isolation and a top surface of the second deep trench isolation;
a first gate electrode disposed on the first gate dielectric layer;
a first source/drain doping region disposed within the substrate, wherein a second part of the first deep trench isolation defines an outer edge of the first source/drain doping region, the first part of the first deep trench isolation is embedded within the first source/drain doping region, and a bottom of the first part of the first deep trench isolation is aligned with a bottom of the second part of the first deep trench isolation;
a second source/drain doping region disposed within the substrate, wherein a second part of the second deep trench isolation defines an outer edge of the second source/drain doping region, the first part of second deep trench isolation is embedded within the second source/drain doping region, and a bottom of the first part of the second deep trench isolation is aligned with a bottom of the second part of the second deep trench isolation;
a first silicide layer covering and contacting the first source/drain doping region;
a second silicide layer covering and contacting the second source/drain doping region; and
a first conductive plate penetrating the first silicide layer and contacting the first source/drain doping region, wherein as seen from a top view, only the first conductive plate penetrates the first silicide layer on the first source/drain doping region, and no other conductive elements penetrate the first silicide layer; and
a second conductive plate penetrating the second silicide layer and contacting the second source/drain doping region;
forming a fin transistor disposed within the low voltage region, wherein the fin transistor comprises:
a fin structure protruding from a second surface of the substrate;
a second gate electrode disposed on the fin structure; and
two shallow trench isolations disposed at two sides of the fin structure.
11 . The fabricating method of a semiconductor device of claim 10 , wherein a first direction is parallel with a long side of the first gate electrode, a second direction is parallel with a short side of the first gate electrode, a third direction is parallel with the short side of the first gate electrode and the third direction is in a reverse direction of the second direction.
12 . The fabricating method of a semiconductor device of claim 11 , wherein along the first direction, a shortest distance between the first conductive plate and an edge of the first silicide layer is between 10 and 90 nanometers.
13 . The fabricating method of a semiconductor device of claim 11 , wherein along the second direction, a shortest distance between the first conductive plate and an edge of the first silicide layer is between 10 and 90 nanometers.
14 . The fabricating method of a semiconductor device of claim 11 , wherein along the third direction, a shortest distance between the first conductive plate and the first gate electrode is between 350 and 1050 nanometers.
15 . The fabricating method of a semiconductor device of claim 10 , wherein a depth of each of the two shallow trench isolations is smaller than a depth of the first deep trench isolation.
16 . The fabricating method of a semiconductor device of claim 10 , wherein there is no epitaxial layer on the first source/drain doping region and the second source/drain doping region.
17 . The fabricating method of a semiconductor device of claim 10 , wherein a voltage of the high voltage transistor is 40 volts.
18 . The fabricating method of a semiconductor device of claim 10 , further comprising a first epitaxial layer and a second epitaxial layer respectively embedded within the fin structure at two sides of the second gate electrode.