Semiconductor device and fabricating method of the same

1 . A semiconductor device, comprising:

a substrate comprising a high voltage region and a low voltage region;

a first deep trench isolation disposed within the high voltage region, wherein the first deep trench isolation comprises:

a first deep trench formed by a first trench and a second trench, wherein the first trench is below the second trench, and wherein the first deep trench comprises a first sidewall and a second sidewall, the first sidewall faces the second sidewall, the first sidewall is formed only by a first plane and a second plane, an edge of the first plane connects to an edge of the second plane, a slope of the first plane is different from a slope of the second plane, and the first plane is a sidewall of the first trench; and

a first insulating layer filling in the first deep trench;

a shallow trench isolation disposed within the low voltage region;

wherein the shallow trench isolation comprises:

a trench disposed on the substrate; and

a second insulating layer filling in the trench, wherein a depth of the shallow trench isolation is smaller than a depth of the first deep trench isolation; and

a fin structure protruding from a second surface of the substrate, wherein a depth of the first trench is the same as a height of the fin structure.

2 . The semiconductor device of claim 1 , wherein the second sidewall of the first deep trench is formed only by a third plane and a fourth plane, an edge of the third plane connects to an edge of the fourth plane, and a slope of the third plane is different from a slope of the fourth plane.

3 . The semiconductor device of claim 1 , wherein the first plane and the second plane contact the first insulating layer, and an angle between the first plane and the second plane is greater than 180 degrees.

4 . The semiconductor device of claim 1 , wherein the first plane and the second plane contact the first insulating layer, and an angle between the first plane and the second plane is smaller than 180 degrees and greater than 90 degrees.

5 . The semiconductor device of claim 1 , further comprising:

a middle voltage region disposed on the substrate;

a second deep trench isolation disposed within the middle voltage region, wherein the second deep trench isolation comprises:

a second deep trench disposed within the substrate, wherein the second deep trench comprises a third sidewall and a fourth sidewall, the third sidewall faces the fourth sidewall, the third sidewall is formed only by a fifth plane and a sixth plane, an edge of the fifth plane connects to an edge of the sixth plane, and a slope of the fifth plane is different from a slope of the sixth plane; and

a third insulating layer filling in the second deep trench, wherein a depth of the second deep trench isolation is the same as the depth of the first deep trench isolation.

6 . The semiconductor device of claim 5 , further comprising:

a high voltage transistor disposed within the high voltage region, wherein the high voltage transistor comprises:

a first gate dielectric layer disposed on a first surface of the substrate and at one side of the first deep trench isolation, and the first gate dielectric layer contacting the first deep trench isolation;

a first gate electrode disposed on the first gate dielectric layer;

a fin transistor disposed within the low voltage region, wherein the fin transistor comprises:

the fin;

a second gate electrode crossing the fin structure; and

a second gate dielectric layer disposed between the fin structure and the second gate electrode;

a middle voltage transistor disposed within the middle voltage region, wherein the middle voltage transistor comprises:

a third gate dielectric layer disposed on a third surface of the substrate; and

a third gate electrode disposed on the third gate dielectric layer.

7 . The semiconductor device of claim 6 , wherein a distance between the first surface and a bottom of the substrate is greater than a distance between the second surface and the bottom of the substrate.

8 . The semiconductor device of claim 1 , wherein the first sidewall only has a first bend, and the second sidewall only has a second bend.