Method for fabricating semiconductor device using patterned mask for forming hard masks on gate structures
A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first transistor region and a second transistor region and then forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, in which the first gate structure includes a first hard mask, the second gate structure includes a second hard mask, and the first hard mask and the second hard mask have different thicknesses. Next, a patterned mask is formed around the first gate structure and the second gate structure, and then part of the first hard mask is removed.
1 . A method for fabricating a semiconductor device, comprising:
providing a substrate having a first transistor region and a second transistor region;
forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, wherein the first gate structure comprises a first hard mask, the second gate structure comprises a second hard mask, and the first hard mask and the second hard mask comprise different thicknesses;
forming a patterned mask around the first gate structure and the second gate structure; and
removing part of the first hard mask and none of the second hard mask.
2 . The method of claim 1 , wherein the substrate comprises a third transistor region, the method further comprising:
forming a third gate structure on the third transistor region, wherein the third gate structure comprises a third hard mask;
forming a first source/drain region adjacent to the first gate structure, a second source/drain region adjacent to the second gate structure, and a third source/drain region adjacent to the third gate structure;
forming a buffer layer on the first gate structure, the second gate structure, and the third gate structure;
forming the patterned mask around the first gate structure, the second gate structure, and the third gate structure;
removing the buffer layer, part of the first hard mask, and part of the third hard mask;
planarizing the first hard mask, the second hard mask, and the third hard mask; and
removing the patterned mask.
3 . The method of claim 2 , further comprising:
forming a contact etch stop layer (CESL) on the buffer layer;
forming an interlayer dielectric (ILD) layer on the CESL; and
performing a replacement metal gate (RMG) process to transform the first gate structure, the second gate structure, and the third gate structure into metal gates.
4 . The method of claim 2 , wherein a width of the first gate structure is less than a width of the third gate structure.
5 . The method of claim 2 , wherein a width of the second gate structure is less than a width of the third gate structure.
6 . The method of claim 1 , wherein a top surface of the second hard mask is lower than a top surface of the first hard mask.
7 . The method of claim 1 , wherein the first transistor region comprises a NMOS region.
8 . The method of claim 1 , wherein the second transistor region comprises a PMOS region.