Vertical PN connection in multi-stack semiconductor device
A multi-stack semiconductor device includes: a substrate; a lower field-effect transistor including a lower channel structure, a lower gate structure surrounding the lower channel structure, and 1 st and 2 nd source/drain regions; and an upper field-effect transistor, on the lower field-effect transistor, including an upper channel structure, an upper gate structure surrounding the upper channel structure, and 3 rd and 4 th source/drain regions vertically above the 1 st and 2 nd source/drain regions, respectively, wherein the 1 st source/drain region is connected to one of a positive voltage source and a negative voltage source, and the 3 rd source/drain region is connected to the other of the positive voltage source and the negative voltage source, and wherein a top portion of the 2 nd source/drain region and a bottom portion the 4 th source/drain region are connected to each other.
1 . A multi-stack semiconductor device comprising:
a substrate;
a lower field-effect transistor comprising a lower channel structure, a lower gate structure surrounding the lower channel structure, and 1 st and 2 nd source/drain regions; and
an upper field-effect transistor, on the lower field-effect transistor, comprising an upper channel structure, an upper gate structure surrounding the upper channel structure, and 3 rd and 4 th source/drain regions vertically above the 1 st and 2 nd source/drain regions, respectively,
wherein the 1 st source/drain region is connected to a 1 st one of a positive voltage source and a negative voltage source, and the 3 rd source/drain region is connected to a 2 nd one of the positive voltage source and the negative voltage source different from the 1 st one,
wherein the multi-stack semiconductor device further comprises a connection structure of which a 1 st end is on a top portion of the 2 nd source/drain region and a 2 nd end is on a bottom portion of the 4 th source/drain region facing the top portion of the 2 nd source/drain region to connect the top portion of the 2 nd source/drain region and the bottom portion of the 4 th source/drain region, and
wherein a width of the 2 nd source/drain region is different from a width of the 4 th source/drain region.
2 . The multi-stack semiconductor device of claim 1 , wherein the connection structure connects the 4 th source/drain region to the 2 nd source/drain region based on an ohmic contact, and
wherein the connection structure comprises a semiconductor material.
3 . The multi-stack semiconductor device of claim 1 , wherein the connection structure comprises a metal or a metal compound,
wherein the top portion of the 2 nd source/drain region comprises a metal ion implanted therein and contacting the 1 st end of the connection structure,
wherein the bottom portion of the 4 th source/drain region comprises another metal ion implanted therein and contacting the 2 nd end of the connection structure.
4 . The multi-stack semiconductor device of claim 1 , further comprising a 1 st contact structure connected to the 2 nd or 4 th source/drain region,
wherein the 1 st contact structure is configured to output an output signal of the multi-stack semiconductor device from the 2 nd or 4 th source/drain region.
5 . The multi-stack semiconductor device of claim 4 , further comprising:
a 2 nd contact structure connecting the 1 st source/drain region to the 1 st one of the positive voltage source and the negative voltage source; and
a 3 rd contact structure connecting the 3 rd source/drain region to the 2 nd one of the positive voltage source and the negative voltage source,
wherein the 2 nd contact structure is at least partially buried in the substrate, and
wherein the 3 rd contact structure is on a top portion of the 3 rd source/drain region.
6 . The multi-stack semiconductor device of claim 1 , further comprising a 1 st contact structure connected to the 2 nd source/drain region, and at least partially buried in the substrate,
wherein the 1 st contact structure is configured to output an output signal of the multi-stack semiconductor device from the 2 nd source/drain region.
7 . The multi-stack semiconductor device of claim 6 , further comprising:
a 2 nd contact structure connecting the 1 st source/drain region to the 1 st one of the positive voltage source and the negative voltage source; and
a 3 rd contact structure connecting the 3 rd source/drain region to the 2 nd one of the positive voltage source and the negative voltage source,
wherein the 2 nd contact structure is at least partially buried in the substrate, and
wherein the 3 rd contact structure is on a top portion of the 3 rd source/drain region.
8 . The multi-stack semiconductor device of claim 1 , wherein the width of the 2 nd source/drain region is greater than the width of the 4 th source/drain region.
9 . The multi-stack semiconductor device of claim 1 , wherein the lower channel structure comprises a lower nanosheet layer, and the upper channel structure comprises an upper nanosheet layer, and
wherein a width of the lower nanosheet layer is different from a width of the upper nanosheet layer.
10 . The multi-stack semiconductor device of claim 9 , wherein the width of the lower nanosheet layer is greater than the width of the upper nanosheet layer.
11 . The multi-stack semiconductor device of claim 9 , wherein the lower nanosheet layer is one of a plurality of lower nanosheet layers included in the lower channel structure,
wherein the upper nanosheet layer is one of a plurality of upper nanosheet layers included in the upper channel structure, and
wherein a number of the plurality of lower nanosheet layers is different from a number of the plurality of upper nanosheet layers.
12 . The multi-stack semiconductor device of claim 11 , wherein the number of the plurality of lower nanosheet layers is less than the number of the plurality of upper nanosheet layers.
13 . A multi-stack semiconductor device comprising:
a lower-stack transistor structure having a 1 st conductivity type; and
an upper-stack transistor structure having a 2 nd conductivity type opposite the 1st conductivity type,
wherein a 1 st source/drain region of the lower-stack transistor structure is provided vertically below a 2 nd source/drain region of the upper-stack transistor structure,
wherein the 1 st source/drain region and the 2 nd source/drain region are connected through a connection structure connecting a metal ion at least partially embedded within a top portion of the 1 st source/drain region and another metal ion at least partially embedded within a bottom portion of the 2 nd source/drain region, and
wherein the connection structure comprises a metal or a metal compound.
14 . The multi-stack semiconductor device of claim 13 , wherein a 1 st end of the connection structure contacts the top portion of the 1 st source/drain region, and a 2 nd end of the connection structure contacts the bottom portion of the 2 nd source/drain region, and
wherein the metal ion at least partially embedded within the top portion of the 1st source/drain region is included in a metal ion implantation structure, with the metal ion implantation structure aligned with the 1 st end of the connection structure.
15 . The multi-stack semiconductor device of claim 13 , further comprising a contact structure connected to the 1 st or 2 nd source/drain region,
wherein the multi-stack semiconductor device is configured to operate as an inverter circuit, and
wherein the contact structure is configured to output an output signal of the inverter circuit.
16 . The multi-stack semiconductor device of claim 15 , wherein the contact structure is connected to the 1 st source/drain region, and at least partially buried in a substrate below the lower-stack transistor structure.
17 . The multi-stack semiconductor device of claim 13 , wherein the metal ion at least partially embedded within the top portion of the 1 st source/drain region is included in a metal ion implantation structure, and
wherein the metal ion implantation structure is spaced apart from opposing side surfaces of the 1 st source/drain region.
18 . A multi-stack semiconductor device comprising:
a substrate;
a lower field-effect transistor on the substrate, the lower field-effect transistor comprising a lower channel structure, a lower gate structure on the lower channel structure, and 1 st and 2 nd source/drain regions;
an upper field-effect transistor on the lower field-effect transistor, the upper field-effect transistor comprising an upper channel structure, an upper gate structure on the upper channel structure, and 3 rd and 4 th source/drain regions; and
a contact structure connected to a bottom portion of the 2 nd source/drain region and at least partially buried in the substrate, the contact structure configured to receive an output signal of the multi-stack semiconductor device via the 2 nd source/drain region and to output the output signal,
wherein the 1 st source/drain region is connected to a 1 st voltage source, and the 3 rd source/drain region is connected to a 2 nd voltage source different from the 1 st voltage source,
wherein a top portion of the 2 nd source/drain region and a bottom portion of the 4 th source/drain region are connected to each other,
wherein the lower channel structure comprises a lower nanosheet layer, and the upper channel structure comprises an upper nanosheet layer, and
wherein a width of the lower nanosheet layer is different from a width of the upper nanosheet layer.
19 . The multi-stack semiconductor device of claim 18 , wherein the multi-stack semiconductor device is configured to operate as an inverter circuit, and
wherein the contact structure is configured to output the output signal of the inverter circuit.
20 . The multi-stack semiconductor device of claim 18 , wherein each of the lower gate structure and the upper gate structure comprises a metal material.