Stacked hybrid TFET and MOSFET
The present disclosure is directed to techniques of fabricating hybrid transistors that combine both TFETs and MOSFETs. The techniques may be commonly integrated such that TFET regions are formed in the same fabrication stages used to fabricate CMOS regions. The TFET and MOSFET may be stacked vertically to reduce the footprint area of the hybrid transistor, which may lead to further semiconductor IC device scaling. The hybrid transistor may utilize a backside power distribution network (BSPDN). The utilization of the BSPDN may reduce resistances, which may result in performance increases. Further, the utilization of the BSPDN may further reduce the footprint area of the hybrid transistor, which may provide for continued scaling. Further, the utilization of the BSPDN may further reduce signal and power potential routing complexities.
1 . A hybrid transistor structure comprising:
a complementary metal oxide semiconductor field effect transistor (MOSFET) comprising first nanolayer channels;
a first source/drain connected to the first nanolayer channels;
a tunneling field effect transistor (TFET) comprising second nanolayer channels wherein the TFET is vertically stacked and aligned above the MOSFET;
a second source/drain connected to the second nanolayer channels;
dielectric isolation region electrically isolating the first source/drain from the second source/drain; and
a third source/drain connected both the first nanolayer channels and the second nanolayer channels.
2 . The hybrid transistor structure of claim 1 , wherein a first width of the first source/drain, a second width of the dielectric isolation region, and a third width of the second source/drain are all substantially equal to one another.
3 . The hybrid transistor structure of claim 1 , wherein a threshold voltage of the TFET is less than a threshold voltage of the MOSFET.
4 . The hybrid transistor structure of claim 1 , wherein the first source/drain is composed of an n-type material, wherein the second source/drain is composed of a p-type material, and wherein the third source/drain is composed of an n-type material.
5 . The hybrid transistor structure of claim 1 , wherein the first source/drain is composed of an p-type material, wherein the second source/drain is composed of a n-type material, and wherein the third source/drain is composed of an p-type material.
6 . The hybrid transistor structure of claim 1 , wherein a topmost surface of the second source/drain is substantially flush with a topmost surface of the third source/drain, and wherein a bottommost surface of the first source/drain is substantially flush with a bottommost surface of the third source/drain.
7 . The hybrid transistor structure of claim 1 , further comprising:
a shared gate surrounding one or more of the first nanolayer channels and one or more of the second nanolayer channels.
8 . A hybrid transistor structure comprising:
a bottom gate all-around transistor comprising bottom nanolayer channels;
a first source/drain connected to the bottom nanolayer channels;
a top gate all-around transistor comprising top nanolayer channels wherein the top gate all-around transistor is vertically stacked and aligned above the bottom gate all-around transistor;
a second source/drain connected to the top nanolayer channels;
dielectric isolation region electrically isolating the first source/drain from the second source/drain;
a third source/drain connected both the bottom nanolayer channels and the top nanolayer channels; and
a placeholder immediately below the third source/drain.
9 . The hybrid transistor structure of claim 8 , wherein a first width of the first source/drain, a second width of the dielectric isolation region, and a third width of the second source/drain are all substantially equal to one another.
10 . The hybrid transistor structure of claim 8 , wherein a threshold voltage of the bottom gate all-around transistor is less than a threshold voltage of the top gate all-around transistor.
11 . The hybrid transistor structure of claim 8 , wherein the first source/drain is composed of an n-type material, wherein the second source/drain is composed of a p-type material, and wherein the third source/drain is composed of an n-type material.
12 . The hybrid transistor structure of claim 8 , wherein the first source/drain is composed of an p-type material, wherein the second source/drain is composed of a n-type material, and wherein the third source/drain is composed of an p-type material.
13 . The hybrid transistor structure of claim 8 , wherein a topmost surface of the second source/drain is substantially flush with a topmost surface of the third source/drain, and wherein a bottommost surface of the first source/drain is substantially flush with a bottommost surface of the third source/drain.
14 . The hybrid transistor structure of claim 8 , further comprising:
a shared gate surrounding one or more of the bottom nanolayer channels and one or more of the top nanolayer channels.
15 . A hybrid transistor structure comprising:
a top transistor vertically stacked and aligned above a bottom transistor;
a first source/drain connected to bottom nanolayer channels of the bottom transistor;
a second source/drain connected to top nanolayer channels of the top transistor;
a third source/drain connected both the bottom nanolayer channels and the top nanolayer channels; and
a liner above and directly contacting a topmost surface of the second source/drain, wherein the liner physically separates from the second source/drain from an interlevel dielectric, and wherein the interlevel dielectric directly contacts a topmost surface of the third source/drain.
16 . The hybrid transistor structure of claim 15 , wherein a threshold voltage of the bottom transistor is less than a threshold voltage of the top transistor.
17 . The hybrid transistor structure of claim 15 , wherein the first source/drain is composed of an n-type material, wherein the second source/drain is composed of a p-type material, and wherein the third source/drain is composed of an n-type material.
18 . The hybrid transistor structure of claim 15 , wherein the first source/drain is composed of an p-type material, wherein the second source/drain is composed of a n-type material, and wherein the third source/drain is composed of an p-type material.
19 . The hybrid transistor structure of claim 15 , wherein a topmost surface of the second source/drain is substantially flush with a topmost surface of the third source/drain, and wherein a bottommost surface of the first source/drain is substantially flush with a bottommost surface of the third source/drain.
20 . The hybrid transistor structure of claim 15 , further comprising:
a shared gate surrounding one or more of the top nanolayer channels and one or more of the bottom nanolayer channels.