IP Library › Granted Patent US 12666712
Granted Patent B2
US 12666712 · App. 18/314,536 · Granted Jun 23, 2026

Integrated circuit and method of forming the same

Inventors: Hui-Zhong Zhuang (Hsinchu, TW); Johnny Chiahoa Li (Hsinchu, TW); Tzu-Ying Lin (Hsinchu, TW); Jia-Hong Gao (Hsinchu, TW); Jung-Chan Yang (Hsinchu, TW); Jerry Chang Jui Kao (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D84/907H03K3/037H10D84/0179H10D84/0186H10D84/038H10D89/10H10D84/937H10D84/966
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Quick Facts
Patent No.
US 12666712
App. No.
18/314,536
Granted
Jun 23, 2026
Kind
B2
Abstract

A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.

Claims (94)

1 . A flip-flop comprising:

a first active region extending in a first direction, and being on a first level of a substrate, the first active region corresponding to a first set of transistors of a first type;

a second active region extending in the first direction, being on the first level, and being separated from the first active region in a second direction different from the first direction, the second active region corresponding to a second set of transistors of a second type different from the first type;

a third active region extending in the first direction, being on the first level, and being separated from the first active region and the second active region in the second direction, the third active region corresponding to a third set of transistors of the second type;

a fourth active region extending in the first direction, being on the first level, and being separated from the first active region, the second active region and the third active region in the second direction, the fourth active region corresponding to a fourth set of transistors of the first type;

a first gate structure extending in the second direction, overlapping the second active region, the third active region and the fourth active region, and being on a second level different from the first level, the first gate structure being configured to receive a first clock signal;

a second gate structure extending in the second direction, overlapping the first active region, and being on the second level, the second gate structure being configured to receive a second clock signal inverted from the first clock signal, and being separated from the first gate structure in the second direction;

a third gate structure extending in the second direction, overlapping the second active region, the third active region and the fourth active region, and being on the second level, the third gate structure being configured to receive the second clock signal, the third gate structure being separated from the first gate structure in the first direction; and

a fourth gate structure extending in the second direction, overlapping the first active region, and being on the second level, the fourth gate structure being configured to receive the first clock signal, and being separated from the third gate structure in the second direction;

wherein the first gate structure and the second gate structure are aligned with each other along a first common axis that extends in the second direction, and

the third gate structure and the fourth gate structure are aligned with each other along a second common axis that extends in the second direction.

2 . The flip-flop of claim 1 , further comprising:

a first contact extending in the second direction, being on a third level different from the first level, and overlapping at least the first active region and the second active region.

3 . The flip-flop of claim 1 , wherein

the first active region has a first width;

the second active region has the first width;

the third active region has a second width different from the first width; and

the fourth active region has the second width.

4 . The flip-flop of claim 1 , wherein

the first active region has a first number of fins;

the second active region has the first number of fins;

the third active region has a second number of fins different from the first number of fins; and

the fourth active region has the second number of fins.

5 . The flip-flop of claim 1 , wherein

the first active region has a first number of nano-sheets;

the second active region has the first number of nano-sheets;

the third active region has a second number of nano-sheets different from the first number of nano-sheets; and

the fourth active region has the second number of nano-sheets.

6 . A flip-flop, comprising:

a first active region extending in a first direction, and being on a first level, the first active region corresponding to a first row of a first set of transistors of a first type, the first active region comprising:

a first portion of the first active region having a first width in a second direction different from the first direction; and

a second portion of the first active region having a second width in the second direction, the second width being different from the first width;

a second active region extending in the first direction, being on the first level, and being separated from the first active region in the second direction, the second active region corresponding to a second row of a second set of transistors of a second type different from the first type, the second active region comprising:

a first portion of the second active region having the first width in the second direction; and

a second portion of the second active region having the second width in the second direction; and

a first dummy gate extending in the second direction, being located on a second level different from the first level, and the first dummy gate separating at least the first portion of the first active region from the second portion of the first active region, or the first portion of the second active region from the second portion of the second active region.

7 . The flip-flop of claim 6 , wherein

the first active region further comprises:

a third portion of the first active region having a third width in the second direction, the third width being different from the first width and the second width; and

the second active region further comprises:

a third portion of the second active region having the third width in the second direction.

8 . The flip-flop of claim 7 , further comprising:

a second dummy gate extending in the second direction, being located on the second level, and being separated from the first dummy gate in the first direction, and the second dummy gate separating at least the second portion of the first active region from the third portion of the first active region, or the second portion of the second active region from the third portion of the second active region.

9 . The flip-flop of claim 8 , further comprising:

a third active region extending in the first direction, and being on the first level, the third active region corresponding to a third row of a third set of transistors of the second type, the third active region comprising:

a first portion of the third active region having the first width in the second direction; and

a second portion of the third active region having the third width in the second direction.

10 . The flip-flop of claim 9 , further comprising:

a fourth active region extending in the first direction, being on the first level, and being separated from the third active region in the second direction, the fourth active region corresponding to a fourth row of a fourth set of transistors of the second type, the fourth active region comprising:

a first portion of the fourth active region having the first width in the second direction; and

a second portion of the fourth active region having the third width in the second direction.

11 . The flip-flop of claim 10 , further comprising:

a third dummy gate extending in the second direction, being located on the second level, and the third dummy gate separating at least the first portion of the third active region from the second portion of the third active region, or the first portion of the fourth active region from the second portion of the fourth active region.

12 . The flip-flop of claim 11 , wherein

the third active region further comprises:

a third portion of the third active region having the first width in the second direction;

the fourth active region further comprises:

a third portion of the fourth active region having the first width in the second direction; and

the flip-flop further comprises:

a fourth dummy gate extending in the second direction, being located on the second level, and being separated from the third dummy gate in the first direction, and the fourth dummy gate separating at least the second portion of the third active region from the third portion of the third active region, or the second portion of the fourth active region from the third portion of the fourth active region.

13 . The flip-flop of claim 12 , further comprising:

a first power rail extending in the first direction, overlapping at least a first set of contacts of the first set of transistors, being configured to supply a first supply voltage to at least the first set of contacts of the first set of transistors, and being on a third level different from the first level and the second level;

a second power rail extending in the first direction, overlapping at least a second set of contacts of the second set of transistors and a third set of contacts of the third set of transistors, being configured to supply a second supply voltage to at least the second set of contacts of the second set of transistors and the third set of contacts of the third set of transistors, being on the third level, and being separated from the first power rail in the second direction; and

a third power rail extending in the first direction, overlapping at least a fourth set of contacts of the fourth set of transistors, being configured to supply the first supply voltage to at least the fourth set of contacts of the fourth set of transistors, being on the third level, and being separated from the first power rail and the second power rail in the second direction,

wherein the second power rail is between the first power rail and the third power rail.

14 . The flip-flop of claim 13 , further comprising:

a first set of conductive lines extending in the first direction, overlapping the first dummy gate, the second dummy gate, the first active region and the second active region, and being on the third level; and

a second set of conductive lines extending in the first direction, overlapping the third dummy gate, the fourth dummy gate, the third active region and the fourth active region, being on the third level, and being separated from the first set of conductive lines in the second direction.

15 . A flip-flop comprising:

a first active region extending in a first direction, and being on a first level of a substrate, the first active region corresponding to a first set of transistors of a first type;

a second active region extending in the first direction, being on the first level, and being separated from the first active region in a second direction different from the first direction, the second active region corresponding to a second set of transistors of a second type different from the first type;

a third active region extending in the first direction, being on the first level, and being separated from the first active region and the second active region in the second direction, the third active region corresponding to a third set of transistors of the second type;

a fourth active region extending in the first direction, being on the first level, and being separated from the first active region, the second active region and the third active region in the second direction, the fourth active region corresponding to a fourth set of transistors of the first type;

a first gate structure extending in the second direction, overlapping the first active region, the second active region, the third active region and the fourth active region, and being on a second level different from the first level, the first gate structure being configured to receive a first clock signal; and

a second gate structure extending in the second direction, overlapping the first active region, the second active region, the third active region and the fourth active region, and being on the second level, the second gate structure being configured to receive a second clock signal inverted from the first clock signal, the second gate structure being separated from the first gate structure in the first direction.

16 . The flip-flop of claim 15 , wherein

the first active region has a first width;

the second active region has the first width;

the third active region has a second width different from the first width; and

the fourth active region has the second width.

17 . The flip-flop of claim 15 , wherein

the first active region has a first number of fins;

the second active region has the first number of fins;

the third active region has a second number of fins different from the first number of fins; and

the fourth active region has the second number of fins.

18 . The flip-flop of claim 15 , wherein

the first active region has a first number of nano-sheets;

the second active region has the first number of nano-sheets;

the third active region has a second number of nano-sheets different from the first number of nano-sheets; and

the fourth active region has the second number of nano-sheets.

19 . The flip-flop of claim 15 , further comprising:

a first contact extending in the second direction, being on a third level different from the first level, and overlapping the first active region and the second active region.

20 . The flip-flop of claim 19 , further comprising:

a second contact extending in the second direction, being on the third level, and overlapping the first active region.