Double side transistors on same silicon wafer
An apparatus and method for efficiently increasing semiconductor chip functionality in a particular area. A semiconductor fabrication process (or process) grows a silicon substrate layer, and forms multiple p-type and n-type transistors along a front side surface of the silicon substrate layer. The process flips the silicon substrate layer and removes silicon substrate leaving a particular thickness of the silicon substrate layer. The process forms multiple p-type and n-type transistors along the back side surface of the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the back side surface to particular signals. The process forms through silicon vias (TSVs) that traverse through the silicon substrate layer. The process again flips the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the front side surface to particular signals.
1 . An integrated circuit comprising:
a first transistor comprising a first source diffusion region;
a silicon substrate layer comprising a first surface stacked adjacent to the first source diffusion region of the first transistor; and
a second transistor comprising a second source diffusion region stacked adjacent to a second surface different from the first surface of the silicon substrate layer; and
wherein responsive to a potential being applied to an input node of a cell of the integrated circuit, a current is conveyed from the input node to an output node of the cell through one of the first transistor and the second transistor.
2 . The integrated circuit as recited in claim 1 , wherein a thickness of the silicon substrate layer:
is measured between the first surface and the second surface along a direction of growth of the silicon substrate layer; and
is greater than a distance that reduces latch up effects of each of the first transistor and the second transistor.
3 . The integrated circuit as recited in claim 1 , wherein:
the first surface is a front side surface of a wafer comprising the silicon substrate layer; and
the second surface is a back side surface of the wafer.
4 . The integrated circuit as recited in claim 3 , wherein a location of a first metal gate of the first transistor is aligned with a location of a second metal gate of the second transistor in a direction of growth of a thickness of the silicon substrate layer.
5 . The integrated circuit as recited in claim 3 , wherein a first terminal of the first transistor is connected to a second terminal of the second transistor by a through silicon via (TSV) that traverses through the silicon substrate layer.
6 . The integrated circuit as recited in claim 3 , wherein each of a first plurality of transistors formed along the first surface of the silicon substrate layer and a second plurality of transistors formed along the second surface of the silicon substrate layer comprises one or more p-type transistors and n-type transistors.
7 . The integrated circuit as recited in claim 3 , wherein the wafer is a silicon on insulator (SOI) wafer with an insulator layer located between the first transistor and the second transistor.
8 . A computing system comprising:
a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks;
an integrated circuit configured to execute the instructions using the source data, wherein the integrated circuit comprises:
a first transistor comprising a first source diffusion region;
a silicon substrate layer comprising a first surface stacked adjacent to the first source diffusion region of the first transistor; and
a second transistor comprising a second source diffusion region stacked adjacent to a second surface different from the first surface of the silicon substrate layer; and
wherein responsive to a potential being applied to an input node of a cell of the integrated circuit, a current is conveyed from the input node to an output node of the cell through one of the first transistor and the second transistor.
9 . The computing system as recited in claim 8 , wherein a thickness of the silicon substrate layer:
is measured between the first surface and the second surface along a direction of growth of the silicon substrate layer; and
is greater than a distance that reduces latch up effects of each of the first transistor and the second transistor.
10 . The computing system as recited in claim 8 , wherein:
the first surface is a front side surface of a wafer comprising the silicon substrate layer; and
the second surface is a back side surface of the wafer.
11 . The computing system as recited in claim 10 , wherein a location of a first metal gate of the first transistor is aligned with a location of a second metal gate of the second transistor in a direction of growth of a thickness of the silicon substrate layer.
12 . The computing system as recited in claim 10 , wherein a first terminal of the first transistor is connected to a second terminal of the second transistor by a through silicon via (TSV) that traverses through the silicon substrate layer.
13 . The computing system as recited in claim 10 , wherein:
a first plurality of transistors formed along the first surface of the silicon substrate layer comprises one or more p-type transistors and n-type transistors; and
a second plurality of transistors formed along the second surface of the silicon substrate layer comprises one or more p-type transistors and n-type transistors.