CMOS structure, and fabrication methods of FinFET CMOS, FD CMOS and GAA CMOS
Provided are a CMOS structure, and fabrication methods of a FinFET CMOS, an FD CMOS and a GAA CMOS. The CMOS structure includes an nMOS and a pMOS, The nMOS includes a first channel region and a first gate electrode formed on a semiconductor substrate, and the pMOS includes a second channel region and a second gate electrode formed on the semiconductor substrate, where the first channel region and the second channel region are formed of semiconductor materials with the same conductivity type, and the first gate electrode and the second gate electrode are formed of the conductive materials with the same work function. This CMOS structure reduces the processing steps for fabricating the CMOS, thereby reducing the process complexity and the production cost, which is beneficial for improving the performance and reliability of CMOS and its integrated circuits.
1 . A complementary metal oxide semiconductor (CMOS) structure, comprising an nMOS and a pMOS, wherein the nMOS comprises a first channel region and a first gate electrode formed on a semiconductor substrate, and the pMOS comprises a second channel region and a second gate electrode formed on the semiconductor substrate;
wherein the first channel region and the second channel region are formed of semiconductor materials with the same conductivity type;
wherein the first gate electrode and the second gate electrode are formed of conductive materials with the same work function;
wherein the CMOS structure is a fin field-effect transistor (FinFET) CMOS;
wherein the first channel region is formed in a first fin, the second channel region is formed in a second fin, and the first fin and the second fin are formed of the semiconductor materials with the same conductivity type and the same doping concentration;
wherein the first gate electrode is located on the first fin, and the second gate electrode is located on the second fin; and
wherein the semiconductor substrate is bulk silicon including a Si substrate layer and a Si epitaxial layer located on the Si substrate layer, the Si substrate layer is one of a p-type material or an n-type material, the Si epitaxial layer is the other of the p-type material or the n-type material, and the first fin and the second fin are formed by the Si epitaxial layer of the bulk silicon.
2 . The CMOS structure according to claim 1 , wherein
materials of the first fin and the second fin are formed of n-type semiconductor materials with the same doping concentration of the Si epitaxial layer of the bulk silicon, a transition structure whose cross section having the same shape and dimension as a cross section of the first fin is disposed at a lower part of the first fin, a material of the transition structure is the p-type material of the Si substrate layer, an n-type semiconductor layer with the same doping concentration as the second fin is formed below the second fin, and the n-type semiconductor layer is formed by the n-type material of the Si epitaxial layer.
3 . The CMOS structure according to claim 1 , wherein
materials of the first fin and the second fin are formed of p-type semiconductor materials with the same doping concentration of the Si epitaxial layer of the bulk silicon, a p-type semiconductor layer with the same doping concentration as the first fin is formed below the first fin, the p-type semiconductor layer is formed by the p-type material of the Si epitaxial layer, a transition structure whose cross section having the same shape and dimension as a cross section of the second fin is reserved at a lower part of the second fin, and a material of the transition structure is the n-type material of the Si substrate layer.
4 . The CMOS structure according to claim 1 , wherein the semiconductor materials of the first channel region and the second channel region are n-type semiconductor materials with the same doping concentration; a first source region and a first drain region of the nMOS are n-type doped; and a second source region and a second drain region of the pMOS are p-type doped.
5 . The CMOS structure according to claim 4 , wherein the work function of the first gate electrode and the second gate electrode is in a range from 4.6 electron-volts (eV) to 5.1 eV.
6 . The CMOS structure according to claim 1 , wherein the semiconductor materials of the first channel region and the second channel region are p-type semiconductor materials with the same doping concentration; a first source region and a first drain region of the nMOS are n-type doped; and a second source region and a second drain region of the pMOS are p-type doped.
7 . The CMOS structure according to claim 6 , wherein the work function of the first gate electrode and the second gate electrode is in a range from 4.1 eV to 4.5 eV.
8 . A fabrication method of a CMOS structure comprising an nMOS and a pMOS, wherein the CMOS structure is a FinFET CMOS, and the fabrication method comprises:
providing a semiconductor substrate;
forming a first fin and a second fin with the same conductivity type on the semiconductor substrate, wherein the first fin comprises a first channel region, and the second fin comprises a second channel region;
forming, on top and sidewall surfaces of the first fin and the second fin, a gate dielectric layer, and a first gate electrode and a second gate electrode with the same work function;
fabricating a first source region and a first drain region in the first fin to form the nMOS;
fabricating a second source region and a second drain region in the second fin to form the pMOS;
wherein the first channel region and the second channel region are formed of semiconductor materials with the same conductivity type;
wherein the first gate electrode and the second gate electrode are formed of conductive materials with the same work function;
wherein the CMOS structure is a fin field-effect transistor (FinFET) CMOS;
wherein the first channel region is formed in a first fin, the second channel region is formed in a second fin, and the first fin and the second fin are formed of the semiconductor materials with the same conductivity type and the same doping concentration;
wherein the first gate electrode is located on the first fin, and the second gate electrode is located on the second fin; and
wherein the semiconductor substrate is bulk silicon including a Si substrate layer and a Si epitaxial layer located on the Si substrate layer, the Si substrate layer is one of a p-type material or an n-type material, the Si epitaxial layer is the other of the p-type material or the n-type material, and the first fin and the second fin are formed by the Si epitaxial layer of the bulk silicon.
9 . The fabrication method according to claim 8 , wherein materials of the first fin and the second fin are formed of n-type semiconductor materials with the same doping concentration of the Si epitaxial layer of the bulk silicon, a transition structure whose cross section having the same shape and dimension as a cross section of the first fin is disposed at a lower part of the first fin, a material of the transition structure is the p-type material of the Si substrate layer, an n-type semiconductor layer with the same doping concentration as the second fin is formed below the second fin, and the n-type semiconductor layer is formed by the n-type material of the Si epitaxial layer.
10 . The fabrication method according to claim 8 , wherein materials of the first fin and the second fin are formed of p-type semiconductor materials with the same doping concentration of the Si epitaxial layer of the bulk silicon, a p-type semiconductor layer with the same doping concentration as the first fin is formed below the first fin, the p-type semiconductor layer is formed by the p-type material of the Si epitaxial layer, a transition structure whose cross section having the same shape and dimension as a cross section of the second fin is reserved at a lower part of the second fin, and a material of the transition structure is the n-type material of the Si substrate layer.