Three-dimensional integrated circuit having ESD protection circuit
An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.
1 . An integrated circuit comprising:
two or more substrates stacked one over another, the two or more substrates including:
a first substrate having an N-type doping;
a second substrate having the N-type doping;
a third substrate having a P-type doping; and
a fourth substrate having the P-type doping;
the first substrate including:
a first dielectric isolation structure electrically separating the first substrate into a first portion surrounded by the first dielectric isolation structure and a second portion outside the first dielectric isolation structure;
a first set of electrical components on one or more substrate of the two or more substrates, the first set of electrical components being configured to form a first circuit;
a first ground reference rail electrically connected to the first circuit;
a first part of a common ground reference rail, the first circuit being connected between a first power supply rail and the first ground reference rail; and
a first electrostatic discharge (ESD) conduction element electrically connected between the first ground reference rail and the first part of the common ground reference rail, the first ESD conduction element including:
a first diode in the first portion of the first substrate, the first diode including a first well having the N-type doping; and
a second diode in the third substrate, the second diode including a second well having the P-type doping;
the first diode and the second diode being electrically connected in parallel and having opposite polarities; and
a second part of the common ground reference rail electrically connected to the third substrate and the fourth substrate.
2 . The integrated circuit of claim 1 , wherein:
the first part of the common ground reference rail is electrically connected to the second part of the common ground reference rail through an electrical path inside the integrated circuit.
3 . The integrated circuit of claim 1 , wherein:
the first part of the common ground reference rail is electrically connected to the second part of the common ground reference rail through an electrical path outside the integrated circuit.
4 . The integrated circuit of claim 1 , wherein:
at least one of the first diode or the second diode is a shallow trench isolation (STI) diode, a gated diode, a well diode, or a metal-oxide semiconductor (MOS) diode.
5 . The integrated circuit of claim 1 , wherein:
the first diode is a P-type diode; and
the second diode is an N-type diode.
6 . The integrated circuit of claim 1 , wherein:
the first substrate is stacked on the third substrate;
the second substrate is stacked on the first substrate; and
the fourth substrate is stacked on the second substrate.
7 . The integrated circuit of claim 1 , wherein:
the first dielectric isolation structure includes silicon dioxide or silicon nitride.
8 . The integrated circuit of claim 1 , wherein:
the first diode includes an anode and a cathode; and
the second diode includes an anode and a cathode; and
the cathode of the first diode being electrically connected to the anode of the second diode, and the anode of the first diode being electrically connected to the cathode of the second diode.
9 . An integrated circuit comprising:
a stack including a first substrate, a second substrate, a third substrate and a fourth substrate;
the first substrate and the fourth substrate each having a P-type doping;
the second substrate and the third substrate each having an N-type doping;
a first part of a common ground reference rail electrically connected to first regions located correspondingly in the first through fourth substrates;
the first regions on the first and third substrates having the N-type doping; and
the first regions on the second and fourth substrates having the P-type doping;
a second part of the common ground reference rail electrically connected to second regions on the first and fourth substrates;
the second regions on the first and fourth substrates having the P-type doping;
the second part of the common ground reference rail being free from being electrically connected to the second and third substrates; and
a first electrostatic discharge (ESD) conduction element between a first ground reference rail of a first circuit and the first part of the common ground reference rail, the first ESD conduction element including:
a first diode between the first region on the first substrate and the first ground reference rail; and
a second diode between the first region on the second substrate and the first ground reference rail.
10 . The integrated circuit of claim 9 , further comprising:
a second ESD conduction element between a second ground reference rail of a second circuit and the first part of the common ground reference rail, the second ESD conduction element including:
a third diode between the first region on the third substrate and the second ground reference rail; and
a fourth diode between the first region on the fourth substrate and the second ground reference rail.
11 . The integrated circuit of claim 9 , wherein:
the first part of the common ground reference rail is electrically connected to the second part of the common ground reference rail through an electrical path inside the integrated circuit.
12 . The integrated circuit of claim 9 , wherein:
the second substrate is stacked on the first substrate;
the third substrate is stacked on the second substrate; and
the fourth substrate is stacked on the third substrate.
13 . The integrated circuit of claim 9 , wherein:
a cathode of the first diode is electrically connected to an anode of the second diode; and
an anode of the first diode is electrically connected to a cathode of the second diode.
14 . The integrated circuit of claim 9 , further comprising:
a third diode on the fourth substrate;
a fourth diode on the second substrate; and
wherein:
a cathode of the third diode is electrically connected to an anode of the fourth diode; and
an anode of the third diode is electrically connected to a cathode of the fourth diode.
15 . An integrated circuit comprising:
two or more substrates stacked one over another, the two or more substrates including:
a first substrate having an N-type doping;
a second substrate having the N-type doping;
a third substrate having a P-type doping; and
a fourth substrate having the P-type doping;
the first substrate including:
a first dielectric isolation structure electrically separating the first substrate into a first portion surrounded by the first dielectric isolation structure and a second portion outside the first dielectric isolation structure;
a first set of electrical components on one or more substrate of the two or more substrates, the first set of electrical components being configured to form a first circuit;
a first ground reference rail electrically connected to the first circuit;
a first part of a common ground reference rail, the first circuit being connected between a first power supply rail and the first ground reference rail; and
a first electrostatic discharge (ESD) conduction element electrically connected between the first ground reference rail and the first part of the common ground reference rail, the first ESD conduction element including:
a first diode in the first portion of the first substrate, the first diode including a first well having the N-type doping; and
a second diode in the third substrate, the second diode including a second well having the P-type doping,
a cathode of the second diode being electrically connected to an anode of the first diode, and
an anode of the second diode being electrically connected to a cathode of the first diode;
the first diode and the second diode being electrically connected in parallel and having opposite polarities; and
a second part of the common ground reference rail electrically connected to the third substrate and the fourth substrate.
16 . The integrated circuit of claim 15 , wherein:
the first part of the common ground reference rail is electrically connected to the second part of the common ground reference rail through an electrical path inside the integrated circuit.
17 . The integrated circuit of claim 15 , wherein:
the first part of the common ground reference rail is electrically connected to the second part of the common ground reference rail through an electrical path outside the integrated circuit.
18 . The integrated circuit of claim 15 , wherein:
at least one of the first diode or the second diode is a shallow trench isolation (STI) diode, a gated diode, a well diode, or a metal-oxide semiconductor (MOS) diode.
19 . The integrated circuit of claim 15 , wherein:
the first diode is a P-type diode; and
the second diode is an N-type diode.
20 . The integrated circuit of claim 15 , wherein:
the first substrate is stacked on the third substrate;
the second substrate is stacked on the first substrate; and
the fourth substrate is stacked on the second substrate.