Stacked CMOS image sensor and method of manufacturing the same
Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor with a high full well capacity (FWC). A first integrated circuit (IC) chip and a second IC chip are stacked with each other. The first IC chip comprises a first semiconductor substrate, and the second IC chip comprises a second semiconductor substrate. A pixel sensor is in and spans the first and second IC chips. The pixel sensor comprises a transfer transistor and a pinned photodiode adjoining the transfer transistor at the first semiconductor substrate, and further comprises a plurality of additional transistors (e.g., a reset transistor, a source-follower transistor, etc.) at the second semiconductor substrate. A bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other and are configured to be biased with different voltages (e.g., a negative voltage and ground).
1 . A method for forming an image sensor, the method comprising:
forming a first integrated circuit (IC) chip, comprising:
forming a photodiode in a first semiconductor substrate;
forming a first transistor on the first semiconductor substrate, adjacent to the photodiode, the photodiode and the first transistor forming a first pixel-sensor portion; and
forming a first interconnect structure covering the first transistor;
forming a second IC chip, wherein the forming of the second IC chip comprises forming a plurality of second transistors on a second semiconductor substrate, and wherein the second transistors comprise a source-follower transistor and form a second pixel-sensor portion;
bonding the first and second IC chips together such that the first and second pixel-sensor portions are stacked and electrically coupled together to form a pixel sensor;
patterning the first semiconductor substrate to form a trench extending laterally along a periphery of the first semiconductor substrate in a closed path surrounding the photodiode and the first transistor, and further extending vertically through the first semiconductor substrate, to separate the first semiconductor substrate into an interior portion and a peripheral portion that are electrically isolated from each other; and
forming a pad at the periphery of the first semiconductor substrate, and in the trench, after the bonding;
wherein the first interconnect structure electrically couples the pad to a bulk of the first semiconductor substrate, wherein the bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other at completion of the bonding, wherein a gate electrode of the source-follower transistor is electrically coupled to a source/drain region of the first transistor at completion of the bonding, wherein the trench exposes a dielectric layer, which separates a gate electrode of the first transistor from the first semiconductor substrate, and wherein a thickness of the dielectric layer at the pad is the same as a separation between the gate electrode of the first transistor and the first semiconductor substrate.
2 . The method according to claim 1 , wherein an anode of the photodiode and a body of the first transistor are not electrically coupled to individual bodies of the second transistors at completion of the bonding.
3 . The method according to claim 1 , wherein the source-follower transistor and the first transistor are configured to concurrently and respectively receive a first transistor-body voltage and a second transistor-body voltage, and wherein the first and second transistor-body voltages are different.
4 . The method according to claim 1 , wherein errant particles extend from the second semiconductor substrate to the peripheral portion of the first semiconductor substrate to electrically short the second semiconductor substrate to the peripheral portion.
5 . The method according to claim 4 , further comprising:
forming a third IC chip, wherein the third IC chip comprises:
forming a plurality of third transistors on a third semiconductor substrate; and
forming a third interconnect structure covering the third transistors, wherein the third transistors and the third interconnect structure form an application-specific integrated circuit (ASIC); and
bonding the second and third IC chips together, such that the second IC chip is between the first and third IC chips and such that the ASIC is electrically coupled to the pixel sensor.
6 . The method according to claim 1 , wherein the bonding comprises both metal-to-metal bonding and dielectric-to-dielectric bonding.
7 . The method according to claim 1 , wherein an anode of the photodiode is electrically coupled to a body of the first transistor.
8 . The method according to claim 1 , further comprising:
forming a plurality of pads, including the pad, on the dielectric layer and spaced from each other in the closed path.
9 . A method for forming an image sensor, comprising:
forming a first integrated circuit (IC) chip comprising a photodetector and a first transistor that border on a first semiconductor substrate;
forming a second IC chip comprising a second transistor on a second semiconductor substrate;
bonding the first and second IC chips together to form a pixel sensor spanning the first and second IC chips, wherein a body of the first transistor is electrically isolated from a body of the second transistor at completion of the bonding;
performing an etch to form a ring-shaped trench dividing the first semiconductor substrate into an inner segment and an outer segment; and
forming a conductive pad in the ring-shaped trench, spaced from the inner and outer segments of the first semiconductor substrate;
wherein errant particles extend from the second semiconductor substrate to the outer segment of the first semiconductor substrate to electrically short the second semiconductor substrate to the outer segment.
10 . The method according to claim 9 , wherein an anode of the photodetector is electrically coupled to the body of the first transistor.
11 . The method according to claim 9 , wherein the forming of the first IC chip comprises:
depositing a dielectric layer fully covering the photodetector;
depositing a conductive layer overlying the dielectric layer;
performing an additional etch into the conductive layer to form a gate electrode bordering the photodetector, wherein the etch stops at a top of the dielectric layer and the gate electrode partially forms the first transistor; and
forming an interconnect structure overlying and electrically coupled to the gate electrode, wherein the dielectric layer fully covers the photodetector after forming the interconnect structure.
12 . The method according to claim 11 , wherein the etch exposes the dielectric layer, which has a thickness at the ring-shaped trench that is the same as a separation between the gate electrode and the first semiconductor substrate.
13 . The method according to claim 9 , further comprising:
forming a third IC chip comprising a third transistor on a third semiconductor substrate; and
bonding the third IC chip to the second IC chip, such that the second IC chip is between the first and third IC chips,
wherein the bonding of the third IC chip to the second IC chip electrically shorts a body of the third transistor to the body of the second transistor.
14 . The method according to claim 9 , wherein the second transistor is formed with a gate dielectric thickness less than a gate dielectric thickness of the first transistor.
15 . The method according to claim 9 , wherein the first transistor is formed with a first gate electrode and a first sidewall spacer on a sidewall of the first gate electrode, wherein the second transistor is formed with a second gate electrode and a second sidewall spacer on a sidewall of the second gate electrode, and wherein a thickness of the first sidewall spacer is greater than a thickness of the second sidewall spacer.
16 . A method for forming an image sensor, comprising:
forming a trench isolation structure extending into a first substrate;
forming a photodetector in the first substrate;
forming a transfer transistor on the first substrate, adjacent to the photodetector, wherein the forming of the transfer transistor comprises: depositing a dielectric layer overlying the trench isolation structure and the first substrate; and forming a gate electrode bordering the photodetector over the dielectric layer;
forming a first interconnect structure overlying and electrically coupled to the transfer transistor;
forming a reset transistor and a source follower transistor on a second substrate;
forming a second interconnect structure overlying and electrically coupled to the reset transistor and the source follower transistor;
electrically coupling the transfer transistor to the reset transistor and the source follower transistor, wherein an anode of the photodetector is electrically isolated from a body of the reset transistor at completion of the electrical coupling;
performing an etch into the first substrate to form a trench, which has a ring-shaped top geometry exposing the dielectric layer at a periphery of the first substrate; and
forming a conductive pad contacting the dielectric layer in the trench, wherein the dielectric layer is entirely formed before the gate electrode is formed.
17 . The method according to claim 16 , further comprising:
forming a first bond structure overlying and electrically coupled to the first interconnect structure; and
forming a second bond structure overlying and electrically coupled to the second interconnect structure, wherein the electrical coupling of the transfer transistor to the reset transistor and the source follower transistor comprises bonding the first and second bond structures together.
18 . The method according to claim 16 , wherein the photodetector, the transfer transistor, the source follower transistor, and the reset transistor form a pixel sensor configured to concurrently receive multiple different transistor-body voltages.
19 . The method according to claim 16 , wherein the trench extends continuously in a closed path along the periphery of the first substrate.
20 . The method according to claim 19 , wherein the dielectric layer is continuous across an entire width of the trench, is continuous from the photodetector to a source/drain region of the transfer transistor that is laterally separated from the photodetector by the gate electrode, and has a thickness at the trench that is the same as a separation from the gate electrode of the first substrate.