High aspect ratio back side deep trench isolaton structure with substrate-embedded metal grid and no pinch off

1 . A method comprising:

providing a semiconductor substrate including a front side, a back side, an image sensing area, a peripheral area, and photodetectors in an array within the image sensing area;

forming first trenches in the back side in a pattern of a grid having segments between the photodetectors;

lining the first trenches with dielectric;

after lining the first trenches with dielectric, depositing an etch stop layer on the back side;

depositing a first passivation layer over the etch stop layer on the back side;

depositing a second passivation layer over the first passivation layer on the back side;

etching second trenches, wherein the second trenches extend through the second passivation layer, through the first passivation layer, through the back side into areas of the first trenches, and stops on the etch stop layer; and

filling the second trenches with metal.

2 . The method of claim 1 , further comprising:

depositing a lower fill material into the first trenches after lining the first trenches with dielectric; and

etching to recess the lower fill material within the first trenches before depositing the etch stop layer.

3 . The method of claim 1 , wherein the second trenches have the pattern of the grid but a smaller width than the first trenches.

4 . The method of claim 1 , wherein:

forming the first trenches comprises using a reticle to photolithographically pattern a first mask; and

forming the second trenches comprises using the reticle to photolithographically pattern a second mask.

5 . The method of claim 4 , wherein the first trenches and the second trenches have different widths.

6 . The method of claim 1 , wherein filling the second trenches with the metal forms a substrate-embedded metal grid, and the method further comprises forming a back side metal grid over the substrate-embedded metal grid.

7 . A method comprising:

providing a semiconductor substrate including a first side and a second side;

forming photodiodes by a process that includes doping the semiconductor substrate through the first side;

forming a back-end-of-line metal interconnect structure on the first side;

bonding the semiconductor substrate to a second substrate;

thinning the semiconductor substrate from the second side;

etching first trenches in the second side, wherein the first trenches are in a first grid pattern and extend into the semiconductor substrate between the photodiodes, and the first trenches are defined by inner sidewalls of the semiconductor substrate;

lining the first trenches with a first dielectric structure;

depositing a second dielectric structure, wherein the second dielectric structure closes off the first trenches;

etching to recess the second dielectric structure within the first trenches;

depositing a third dielectric structure in the first trenches;

after depositing the third dielectric structure, etching second trenches in a second grid pattern, wherein the second grid pattern is aligned with the first grid pattern, and the second trenches extend into the first trenches; and

depositing a metal in the second trenches.

8 . The method of claim 7 , wherein the first dielectric structure comprises a high-k dielectric layer, and the second dielectric structure comprises silicon dioxide.

9 . The method of claim 7 , wherein depositing the third dielectric structure comprises sequentially depositing an additional dielectric layer and a silicon dioxide layer, wherein the additional dielectric layer has a refractive index intermediate between that of silicon dioxide and that of the semiconductor substrate.

10 . The method of claim 9 , wherein the first additional dielectric layer comprises tantalum pentoxide.

11 . The method of claim 7 , wherein etching to recess the second dielectric structure within the first trenches removes the second dielectric structure from above the first dielectric structure on the second side.

12 . The method of claim 7 , wherein etching to recess the second dielectric structure comprises a wet etch process.

13 . The method of claim 7 , wherein etching to recess the second dielectric structure restricts the second dielectric structure to a lower half of the first trenches.

14 . The method of claim 7 , further comprising, after etching to recess the second dielectric structure and before depositing the third dielectric structure in the first trenches, depositing an etch stop layer in the first trenches.

15 . The method of claim 7 , wherein etching the second trenches comprises anisotropic plasma etching.

16 . The method of claim 7 , wherein:

etching the first trenches in a first grid pattern comprises using a reticle in a first photolithographic process to pattern a first mask; and

etching the second trenches in a second grid pattern comprises using the reticle in a second photolithographic process to pattern a second mask.

17 . The method of claim 7 , wherein the metal forms a substrate-embedded metal grid, and the method further comprises forming a back side metal grid over the substrate-embedded metal grid.

18 . The method of claim 7 , wherein the third dielectric structure comprises an etch stop layer and a passivation layer over the etch stop layer, and etching the second trenches in the second grid pattern is etching that stops on the etch stop layer.

19 . A method comprising:

providing a semiconductor substrate including a first side and a second side;

forming photodiodes by a process that includes doping the semiconductor substrate through the first side;

forming a back-end-of-line metal interconnect structure on the first side;

bonding the semiconductor substrate to a second substrate;

thinning the semiconductor substrate from the second side;

etching first trenches in the second side, wherein the first trenches are defined by inner sidewalls of the semiconductor substrate;

using a conformal deposition process to deposit one or more high-k dielectric layers on the inner sidewalls;

filling the first trenches with an oxide;

etching to remove the oxide from an upper portion of the first trenches;

filling the first trenches by depositing one or more additional dielectric layers;

etching second trenches, wherein the second trenches extend through the one or more additional dielectric layers and into the first trenches; and

depositing metal in the second trenches.

20 . The method of claim 19 , further comprising forming a back side metal grid, wherein the back side metal grid is grounded to the semiconductor substrate.