Image acquisition device
An image sensor includes photodetection pixels formed inside and on top of a semiconductor substrate. An interconnection network coats a surface of the semiconductor substrate. The interconnection network includes a level of conductive vias in contact, by their lower surface, with the photodetection pixels. The conductive vias are made of doped polysilicon and have a heavier doping on their lower surface side than on their upper surface side.
1 . An image sensor, comprising:
photodetection pixels formed inside and on top of a semiconductor substrate; and
an interconnection network over a surface of the semiconductor substrate, the interconnection network comprising conductive vias, wherein lower surfaces of the conductive vias are in electrical contact with the photodetection pixels;
wherein each conductive via is made of doped polysilicon; and
wherein the doped polysilicon has a heavier doping at the lower surface of the conductive via than at an upper surface of the conductive via.
2 . The sensor according to claim 1 , wherein doping of each conductive via has a decreasing doping gradient starting from the lower surface towards the upper surface.
3 . The image sensor according to claim 1 , wherein each conductive via is doped with phosphorus or arsenic atoms.
4 . An image acquisition device, comprising:
a first image sensor comprising:
first photodetection pixels formed inside and on top of a first semiconductor substrate; and
an interconnection network over a surface of the first semiconductor substrate, the interconnection network comprising conductive vias, wherein lower surfaces of the conductive vias are in electrical contact with the first photodetection pixels;
wherein each conductive via is made of doped polysilicon; and
wherein the doped polysilicon has a heavier doping at the lower surface of the conductive via than at an upper surface of the conductive via; and
a second image sensor comprising second photodetection pixels formed inside and on top of a second semiconductor substrate;
wherein the first image sensor and the second image sensor are stacked.
5 . The image acquisition device of claim 4 , wherein the first photodetection pixels are configured for detection of visible light colors and the second photodetection pixels are configured for detection of infrared light.
6 . The image acquisition device of claim 4 , wherein an interconnection network of the second image sensor is in contact with the interconnection network of the first image sensor.
7 . The image acquisition device of claim 4 , wherein doping of each conductive via has a decreasing doping gradient starting from the lower surface towards the upper surface.
8 . The image acquisition device of claim 4 , wherein each conductive via is doped with phosphorus or arsenic atoms.
9 . A method of manufacturing an image sensor, comprising:
forming photodetection pixels inside and on top of a semiconductor substrate; and
forming a level of an interconnection network including conductive vias;
wherein lower surfaces of the conductive vias are in contact with the photodetection pixels;
wherein each conductive via is made of doped polysilicon; and
wherein the doped polysilicon has a heavier doping at the lower surface of the conductive via than at an upper surface of the conductive via.
10 . The method according to claim 9 , wherein each conductive via has a decreasing doping gradient starting from the lower surface towards the upper surface.
11 . The method according to claim 9 , wherein forming the level of the interconnection network including conductive vias comprises forming openings in an insulating layer, said openings extending to contact the photodetection pixels.
12 . The method according to claim 11 , wherein the forming the level of the interconnection network including conductive vias further comprises:
forming an amorphous silicon film on top of the insulating layer and inside the openings;
ex-situ doping of said amorphous silicon film by implantation of dopants; and
filling the openings with an amorphous silicon layer.
13 . The method according to claim 12 , wherein said amorphous silicon film, after ex-situ doping, has a doping in the order of 1×10 21 at/cm 3 .
14 . The method according to claim 13 , wherein forming the amorphous silicon film comprises performing an in-situ doping during deposition of the amorphous silicon film.
15 . The method according to claim 13 , wherein filling the openings with the amorphous silicon layer comprises performing an in-situ doping during deposition of the amorphous silicon layer.
16 . The method according to claim 11 , further comprising, after forming the openings:
filling the openings with an amorphous silicon layer; and
ex-situ doping of said amorphous silicon layer by implantation of dopants at a portion of said amorphous silicon layer located in a vicinity of the semiconductor substrate.
17 . The method according to claim 16 , further comprising in-situ doping of the amorphous silicon layer during deposition.
18 . The method according to claim 16 , wherein said amorphous silicon layer has a doping in the order of 1×10 21 at/cm 3 at a vicinity of the semiconductor substrate.
19 . The method according to claim 11 , further comprising, after forming the openings, performing an amorphization of a surface of the semiconductor substrate and of a surface of polysilicon conductive gates at the bottom of the openings.