Array substrate, testing method and manufacturing method thereof, and displaying device
View Patent ↗An array substrate, a testing method and manufacturing method thereof, and a displaying device. According to the disclosure, a plurality of test capacitors connected in parallel, a first connecting wire, a second connecting wire, a first test terminal and a second test terminal are arranged in an array substrate located in a test area, each test capacitor comprises a first electrode, a first insulating layer and a second electrode which are stacked on a base, and each test capacitor has the same film structure as a storage capacitor arranged in an active area. By making the first electrode of each test capacitor in the test area connected to the first test terminal through the first connecting wire, and the second electrode of each test capacitor connected to the second test terminal through the second connecting wire, the plurality of test capacitors are connected in parallel.
1 . An array substrate, comprising a test area;
wherein the array substrate located in the test area comprises a plurality of test capacitors connected in parallel, a first connecting wire, a second connecting wire, a first test terminal and a second test terminal;
each of the test capacitors comprises a first electrode, a first insulating layer and a second electrode which are disposed in layer configuration on a base, and an overlapping area exists between an orthographic projection of the first electrode on the base and an orthographic projection of the second electrode on the base, wherein the first electrode of each of the test capacitors is located in a first electrode layer, and the second electrode of each of the test capacitors is located in a second electrode layer;
the first electrode of each of the test capacitors is connected to the first test terminal through the first connecting wire, and the second electrode of each of the test capacitors is connected to the second test terminal through the second connecting wire; and
the array substrate located in the test area further comprises a second insulating layer disposed on a side, away from the first insulating layer, of the second electrode layer, and a third electrode layer disposed on a side, away from the second electrode layer, of the second insulating layer, the first connecting wire is connected to the first electrode of each of the test capacitors through a first via hole penetrating through the second insulating layer and the first insulating layer, and each of the second electrodes has a seventh via hole, the first via hole is located in an area enclosed by the seventh via hole, and the first via hole and the second electrode are separated by the second insulating layer.
2 . The array substrate according to claim 1 , wherein the first connecting wire, the first test terminal and the second test terminal are all located in the third electrode layer, and the second connecting wire is located in the second electrode layer; and
the second connecting wire and the second electrode of each of the test capacitors are disposed on a same layer and connected to each other, and the second test terminal is connected to the second connecting wire through a second via hole penetrating through the second insulating layer.
3 . The array substrate according to claim 1 , wherein an orthographic projection of the first via hole and the seventh via hole on the base are annular.
4 . The array substrate according to claim 1 , wherein in the test area, no overlapping area exists between an orthographic projection of the first connecting wire on the base and an orthographic projection of the second connecting wire on the base.
5 . The array substrate according to claim 1 , further comprising a dummy area surrounding the test area;
the array substrate located in the dummy area comprises a plurality of dummy capacitors, and the plurality of dummy capacitors surround the test capacitor disposed in the test area; and
each of the dummy capacitors comprises a fifth electrode, the first insulating layer and a sixth electrode which are disposed in layer configuration, the fifth electrode is disposed on a same layer as the first electrode, the sixth electrode is disposed on a same layer as the second electrode, and an overlapping area exists between an orthographic projection of the fifth electrode on the base and an orthographic projection of the sixth electrode on the base.
6 . The array substrate according to claim 1 , wherein the plurality of test capacitors located in the test area are distributed in an array.
7 . The array substrate according to claim 1 , wherein in a row direction along the array substrate, a first size of two adjacent test capacitors is 30-40 μm; and
in a column direction of the array substrate, a second size of two adjacent test capacitors is 60-70 μm.
8 . The array substrate according to claim 1 , wherein the first electrode layer is a first grid layer, the second electrode layer is a second grid layer, the first insulating layer is the first grid insulating layer, the second insulating layer is an interlayer dielectric layer, and the third electrode layer is a source-drain electrode layer; and
an active layer and a second grid insulating layer are further disposed between the base and the first grid layer, and the second grid insulating layer is located on a side, away from the base, of the active layer.
9 . A testing method of an array substrate, wherein the method is configured to the array substrate according to claim 1 , and comprising:
inputting a scanning signal to the second electrode of each of the capacitors through the second test terminal;
receiving an induction signal output by the first electrode of each of the test capacitors through a first test terminal; and
determining a ratio of a practical value of capacitance corresponding to the induction signal to the number of the test capacitors as a value of capacitance for each of the test capacitors.
10 . A manufacturing method of an array substrate, comprising:
providing a base, the base comprising a test area;
forming a plurality of first electrodes on the base in the test area;
forming a first insulating layer covering the first electrode and the base; and
forming a plurality of second electrodes on the first insulating layer in the test area to obtain a plurality of test capacitors connected in parallel; and
wherein an overlapping area exists between an orthographic projection of each of the first electrodes on the base and an orthographic projection of the second electrode on the base, wherein the first electrode of each of the test capacitors is located in a first electrode layer, and the second electrode of each of the test capacitors is located in a second electrode layer;
the first electrode of each of the test capacitors is connected to a first test terminal through a first connecting wire, and the second electrode of each of the test capacitors is connected to a second test terminal through a second connecting wire; and
the array substrate located in the test area further comprises a second insulating layer disposed on a side, away from the first insulating layer, of the second electrode layer, and a third electrode layer disposed on a side, away from the second electrode layer, of the second insulating layer, the first connecting wire is connected to the first electrode of each of the test capacitors through a first via hole penetrating through the second insulating layer and the first insulating layer, and each of the second electrodes has a seventh via hole, the first via hole is located in an area enclosed by the seventh via hole, and the first via hole and the second electrode are separated by the second insulating layer.
11 . A displaying device, comprising the array substrate according to claim 1 .