MRAM bottom electrode shroud

1 . A memory device, comprising:

a lower level line in a lower dielectric layer, wherein a top surface of the lower level line and a top surface of the lower dielectric layer are substantially coplanar;

a bottom electrode composed of a first conductive material in electrical contact with the lower level line, the bottom electrode having an uppermost surface, a first sidewall, and a second sidewall;

a dielectric layer upon the lower dielectric layer, the dielectric layer directly upon the uppermost surface and directly upon the first and second sidewalls of the bottom electrode such that an uppermost surface of the dielectric layer is arranged higher than the uppermost surface of the bottom electrode;

a metal body composed of a second conductive material different from the first conductive material in direct contact with the uppermost surface of the bottom electrode and inset between the first sidewall and the second sidewall, the metal body further extending through the dielectric layer to the uppermost surface of the dielectric layer such that the dielectric layer shrouds a side perimeter of the metal body; and

a magnetic tunnel junction memory component comprising a bottom ferromagnetic plate, a top ferromagnetic plate, and an insulating layer between the bottom ferromagnetic plate and the top ferromagnetic plate, the bottom ferromagnetic plate arranged in direct contact with the metal body and in direct contact with the uppermost surface of the dielectric layer, wherein the metal body is inset between respective sidewalls of the magnetic tunnel junction memory component.

2 . The memory device of claim 1 , wherein:

a lowermost surface of the bottom electrode is substantially coplanar with a lowermost surface of the dielectric layer.

3 . The memory device of claim 1 , wherein:

the dielectric layer is in direct contact with the uppermost surface, the first sidewall, and the second sidewall of the bottom electrode.

4 . The memory device of claim 1 , wherein:

the magnetic tunnel junction memory component is separated from the uppermost surface of the bottom electrode by the dielectric layer and by the metal body.

5 . The memory device of claim 1 , wherein:

a width of the bottom electrode extends from the first sidewall of the bottom electrode to the second sidewall of the bottom electrode;

a width of the metal body extends from a first sidewall of the metal body to a second sidewall of the metal body; and

the width of the metal body is less than the width of the bottom electrode.

6 . The memory device of claim 5 , wherein:

neither of the first and second sidewalls of the bottom electrode is substantially coplanar with either of the first and second sidewalls of the metal body.

7 . The memory device of claim 5 , wherein:

the first sidewall of the metal body is arranged laterally inwardly relative to the first sidewall of the bottom electrode; and

the second sidewall of the metal body is arranged laterally inwardly relative to the second sidewall of the bottom electrode.

8 . The memory device of claim 7 , wherein:

a first region of the dielectric layer is in direct contact with the first sidewall of the metal body, the uppermost surface of the bottom electrode, and a lowermost surface of the magnetic tunnel junction memory component such that the first region is interposed between the uppermost surface of the bottom electrode and the lowermost surface of the magnetic tunnel junction memory component; and

a second region of the dielectric layer is in direct contact with the second sidewall of the metal body, the uppermost surface of the bottom electrode, and the lowermost surface of the magnetic tunnel junction memory component such that the second region is interposed between the uppermost surface of the bottom electrode and the lowermost surface of the magnetic tunnel junction memory component.

9 . A method of making memory device, the method comprising:

forming a lower level line in a lower dielectric layer, wherein a top surface of the lower level line and a top surface of the lower dielectric layer are substantially coplanar;

forming a bottom electrode composed of a first conductive material upon the lower level line, the bottom electrode having an uppermost surface, a first sidewall, and a second sidewall;

forming a dielectric layer directly upon the uppermost surface and directly upon the first and second sidewalls of the bottom electrode such that an uppermost surface of the dielectric layer is arranged higher than the uppermost surface of the bottom electrode;

forming a metal body composed of a second conductive material different from the first conductive material in direct contact with the uppermost surface of the bottom electrode and inset between the first sidewall and the second sidewall, the metal body further extending through the dielectric layer to the uppermost surface of the dielectric layer such that the dielectric layer shrouds a side perimeter of the metal body; and

forming a magnetic tunnel junction memory component comprising a bottom ferromagnetic plate, a top ferromagnetic plate, and an insulating layer between the bottom ferromagnetic plate and the top ferromagnetic plate, the bottom ferromagnetic plate arranged in direct contact with the metal body and in direct contact with the uppermost surface of the dielectric layer, wherein the metal body is inset between respective sidewalls of the magnetic tunnel junction memory component.

10 . The method of claim 9 , wherein:

forming the metal body includes:

forming an opening in the dielectric layer above the bottom electrode; and

filling the opening with metal.

11 . The method of claim 10 , wherein:

forming the opening includes forming the opening such that a width of the opening is narrower than a width of the bottom electrode.

12 . A memory device, comprising:

a lower level line in a lower dielectric layer, wherein a top surface of the lower level line and a top surface of the lower dielectric layer are substantially coplanar;

a bottom electrode composed of a first conductive material in electrical contact with the lower level line, the bottom electrode having an uppermost surface, a first sidewall, and a second sidewall;

a dielectric layer upon the lower dielectric layer, the dielectric layer directly upon the uppermost surface and directly upon the first and second sidewalls of the bottom electrode such that an uppermost surface of the dielectric layer is arranged higher than the uppermost surface of the bottom electrode;

a metal body composed of a second conductive material different from the first conductive material in direct contact with the uppermost surface of the bottom electrode and inset between the first sidewall and the second sidewall, the metal body further extending through the dielectric layer to the uppermost surface of the dielectric layer, wherein the dielectric layer forms a bottom electrode shroud around the metal body by electrically separating the first and second sidewalls of the bottom electrode from one or more side surface(s) of the metal body; and

a magnetic tunnel junction memory component comprising a bottom ferromagnetic plate, a top ferromagnetic plate, and an insulating layer between the bottom ferromagnetic plate and the top ferromagnetic plate, the bottom ferromagnetic plate, the bottom ferromagnetic plate arranged in direct contact with the metal body and in direct contact with the uppermost surface of the dielectric layer, wherein the metal body is inset between respective sidewalls of the magnetic tunnel junction memory component.

13 . The memory device of claim 12 , wherein:

a lowermost surface of the bottom electrode is substantially coplanar with a lowermost surface of the dielectric layer.

14 . The memory device of claim 12 , wherein:

the dielectric layer is in direct contact with the uppermost surface, the first sidewall, and the second sidewall of the bottom electrode.