IP Library Granted Patent US 12666883
Granted Patent B2
US 12666883 · App. 18/317,268 · Granted Jun 23, 2026

Direct non-ohmic switch for voltage instability protection and methods for forming the same

Inventors: Wei Ting Hsieh (Hsinchu, TW); Kuo-Ching Huang (Hsinchu City, TW); Yu-Wei Ting (Taipei City, TW); Ching-En Chen (Chiayi City, TW); Kuo-Pin Chang (Zhubei City, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
H10N79/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12666883
App. No.
18/317,268
Granted
Jun 23, 2026
Kind
B2
Abstract

A device structure includes semiconductor devices located on a substrate; metal interconnect structures located in dielectric material layers overlying the semiconductor devices; and a non-Ohmic voltage-triggered switch including a first switch electrode that is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures, a second switch electrode, and a non-Ohmic switching material portion providing a non-Ohmic current-voltage characteristics and in contact with the first switch electrode and the second switch electrode. The non-Ohmic voltage-triggered switch may be used as an electrostatic discharge (ESD) switch.

Claims (69)

1 . A device structure comprising:

semiconductor devices located on a substrate;

metal interconnect structures located in dielectric material layers overlying the semiconductor devices, wherein the metal interconnect structures comprise:

a first conductive line structure; and

a second conductive line structure, wherein:

the first conductive line structure and the second conductive line structure are formed within a first dielectric material layer selected from the dielectric material layers and are spaced by a gap therebetween;

a first sidewall of the first conductive line structure and a second sidewall of the second conductive line structure face the gap;

top surfaces of the first conductive line structure and the second conductive line structure are located within a horizontal plane including a top surface of the first dielectric material layer;

a volume of a via cavity which is not filled with the first dielectric material layer, the first conductive line structure, or the second conductive line structure is present in the gap, the volume of the via cavity being defined by, and bounded by, the first sidewall of the first conductive line structure, the second sidewall of the second conductive line structure, sidewalls of the first dielectric material layer, a recessed surface of the first dielectric material layer, and the horizontal plane; and

one of the sidewalls of the first dielectric material layer vertically extends downward from the first sidewall to the recessed surface and another of the sidewalls of the first dielectric material layer vertically extends downward from the second sidewall to the recessed surface; and

a non-Ohmic voltage-triggered switch comprising:

a first switch electrode that comprises the first conductive line structure and is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures;

a second switch electrode that comprises the second conductive line structure; and

a non-Ohmic switching material portion located at least partly within the volume of the via cavity and contacting the recessed surface of the first dielectric material layer and electrically connected to the first switch electrode and the second switch electrode, wherein the non-Ohmic switching material portion has non-Ohmic current-voltage characteristics.

2 . The device structure of claim 1 , wherein the non-Ohmic switching material portion comprises a sidewall surface segment that contacts said one of the sidewalls of the first dielectric material layer.

3 . The device structure of claim 2 , wherein the non-Ohmic switching material portion comprises:

a first additional sidewall surface segment that contacts a sidewall of the first switch electrode; and

a second additional sidewall surface segment that contacts a sidewall of the second switch electrode.

4 . The device structure of claim 3 , wherein the non-Ohmic switching material portion has a top surface located at, or below, a horizontal plane including top surfaces of the first switch electrode and the second switch electrode.

5 . The device structure of claim 1 , wherein the non-Ohmic switching material portion comprises an ovonic threshold material or a phase change memory material.

6 . A device structure comprising:

semiconductor devices located on a substrate;

metal interconnect structures located in dielectric material layers overlying the semiconductor devices, wherein the metal interconnect structures comprise:

a first conductive line structure; and

a second conductive line structure, wherein:

the first conductive line structure and the second conductive line structure are formed within a first dielectric material layer selected from the dielectric material layers and are spaced by a gap therebetween;

a first sidewall of the first conductive line structure and a second sidewall of the second conductive line structure face the gap;

top surfaces of the first conductive line structure and the second conductive line structure are located within a horizontal plane including a top surface of the first dielectric material layer;

a volume of a via cavity which is not filled with the first dielectric material layer, the first conductive line structure, or the second conductive line structure is present in the gap, the volume of the via cavity being defined by, and bounded by, the first sidewall of the first conductive line structure, the second sidewall of the second conductive line structure, sidewalls of the first dielectric material layer, a recessed surface of the first dielectric material layer, and the horizontal plane; and

one of the sidewalls of the first dielectric material layer vertically extends downward from the first sidewall to the recessed surface and another of the sidewalls of the first dielectric material layer vertically extends downward from the second sidewall to the recessed surface;

an electrostatic discharge line overlying the first dielectric material layers; and

an electrostatic discharge (ESD) switch overlying the first dielectric material layers comprising:

a first switch electrode that comprises the first conductive line structure and is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures;

a second switch electrode that comprises the second conductive line structure and is electrically connected to the electrostatic discharge line; and

a non-Ohmic switching material portion that has non-Ohmic current-voltage characteristics and is in contact with the first switch electrode and the second switch electrode and is located at least partly within the volume of the via cavity and contacts the recessed surface of the first dielectric material layer, wherein the non-Ohmic switching material portion comprises an ovonic threshold material or a phase change memory material.

7 . The device structure of claim 6 , wherein:

the first switch electrode and the second switch electrode further comprise metal plates located on a respective one of the first conductive line structure and the second conductive line structure; and

the non-Ohmic switching material portion contacts sidewalls of the first switch electrode and the second switch electrode.

8 . A device structure comprising:

semiconductor devices located on a substrate;

metal interconnect structures located in dielectric material layers overlying the semiconductor devices, wherein the metal interconnect structures comprise:

a first conductive line structure; and

a second conductive line structure, wherein:

the first conductive line structure and the second conductive line structure are formed within a first dielectric material layer selected from the dielectric material layers and are spaced by a gap therebetween;

a first sidewall of the first conductive line structure and a second sidewall of the second conductive line structure face the gap;

top surfaces of the first conductive line structure and the second conductive line structure are located within a horizontal plane including a top surface of the first dielectric material layer;

a volume of a via cavity which is not filled with the first dielectric material layer, the first conductive line structure, or the second conductive line structure is present in the gap, the volume of the via cavity being defined by, and bounded by, the first sidewall of the first conductive line structure, the second sidewall of the second conductive line structure, sidewalls of the first dielectric material layer, a recessed surface of the first dielectric material layer, and the horizontal plane; and

one of the sidewalls of the first dielectric material layer vertically extends downward from the first sidewall to the recessed surface and another of the sidewalls of the first dielectric material layer vertically extends downward from the second sidewall to the recessed surface;

a first switch electrode that comprises the first conductive line structure and is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures;

a second switch electrode that comprises the second conductive line structure; and

a non-Ohmic switching material portion having a non-Ohmic current-voltage characteristics and in contact with the first switch electrode and the second switch electrode and located at least partly within the volume of the via cavity and in contact with the recessed surface of the first dielectric material layer, wherein the non-Ohmic switching material portion comprises an ovonic threshold material or a phase change memory material and is embedded in one of the dielectric material layers.

9 . The device structure of claim 8 , wherein the non-Ohmic switching material portion comprises a non-Ohmic switching material via structure having a bottom surface that contacts a dielectric surface of one of the dielectric material layers.

10 . The device structure of claim 9 , wherein the non-Ohmic switching material via structure comprises a first additional sidewall surface segment that contacts a sidewall of the first switch electrode and a second additional sidewall surface segment that contacts a sidewall of the second switch electrode.

11 . The device structure of claim 8 , wherein:

the first switch electrode further comprises a first metal plate located on a top surface and a sidewall of a first conductive line structure; and

the second switch electrode further comprises a second metal plate located on a top surface and a sidewall of a second conductive line structure.

12 . The device structure of claim 11 , wherein the first metal plate and the second metal plate comprise an electroplatable metallic material selectively located on the conductive line structures.

13 . The device structure of claim 8 , wherein the non-Ohmic switching material portion has a top surface located at, or below, a horizontal plane including top surfaces of the first switch electrode and the second switch electrode.

14 . The device structure of claim 8 , wherein the first switch electrode and the second switch electrode further comprise a metallic material selectively disposed on physically exposed surfaces of the first conductive line structure and the second conductive line structure underlying conductive line structures.

15 . The device structure of claim 8 , further comprising an electrostatic discharge line electrically connected to the second switch electrode, wherein the electrostatic discharge line is a component of an electrostatic discharge path.

16 . The device structure of claim 1 , wherein:

the first switch electrode comprises a first metal plate located on the top surface and the first sidewall of the first conductive line structure; and

the second switch electrode comprises a second metal plate located on the top surface and the second sidewall of the second conductive line structure.

17 . The device structure of claim 1 , wherein the non-Ohmic switching material portion comprises a non-Ohmic switching material via structure having a bottom surface that contacts the recessed surface of the first dielectric material layer and a first additional sidewall surface segment that contacts the first sidewall of the first switch electrode and a second additional sidewall surface segment that contacts the second sidewall of the second switch electrode.

18 . The device structure of claim 6 , wherein:

the first switch electrode comprises a first metal plate located on the first conductive line structure; and

the second switch electrode comprises a second metal plate located on the second conductive line structure.

19 . The device structure of claim 6 , wherein the non-Ohmic switching material portion comprises a non-Ohmic switching material via structure having a bottom surface that contacts the recessed surface of the first dielectric material layer and a first additional sidewall surface segment that contacts the first sidewall of the first switch electrode and a second additional sidewall surface segment that contacts the second sidewall of the second switch electrode.

20 . The device structure of claim 6 , wherein the non-Ohmic switching material portion comprises a non-Ohmic switching material via structure located within the volume of the via cavity and having a horizontal top surface.