IP Library › Granted Patent US 12666935

Granted Patent B2

US 12666935 · App. 17/656,366 · Granted Jun 23, 2026

Implantation through an etch stop layer

Inventors: Moshe Dolejsi (Portland, OR); Harish Ganapathy (Portland, OR); Travis W. Lajoie (Forest Grove, OR); Deepyanti Taneja (Happy Valley, OR); Huiying Liu (Portland, OR); Cheng Tan (Hillsboro, OR); Timothy Jen (Portland, OR); Van H. Le (Beaverton, OR); Abhishek A. Sharma (Portland, OR)

Assignee: INTEL CORPORATION

H10W20/074 H10B12/033 H10W20/051 H10W20/42

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Quick Facts

Patent No.: US 12666935
App. No.: 17/656,366
Granted: Jun 23, 2026
Kind: B2

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Abstract

An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

Claims (57)

1 . An integrated circuit comprising:

a first layer comprising dielectric material, and one or both of an interconnect feature and a device within the dielectric material of the first layer;

a second layer above the first layer, the second layer comprising dielectric material, and one or both of an interconnect feature and a device within the dielectric material of the second layer; and

a third layer between the first layer and the second layer, the third layer having a thickness between the first and second layers in the range of 0.5 to 50 nanometers; and

an impurity within the first layer and the third layer, the impurity having a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer,

wherein the dielectric material of the first layer comprises a first section and a second section, the first section laterally adjacent to the second section within the dielectric material of the first layer, the impurity within the first section is at a first average depth from a surface of the third layer, and the impurity within the second section is at a second average depth from the surface of the third layer, wherein the first average depth is more than the second average depth.

2 . The integrated circuit of claim 1 , wherein the third layer is an etch stop layer.

3 . The integrated circuit of claim 1 , wherein the first layer and/or the second layer is an interconnect layer.

4 . The integrated circuit of claim 1 , wherein the impurity is not present in the second layer.

5 . The integrated circuit of claim 1 , wherein the interconnect feature of the first layer is a first interconnect feature, and wherein the integrated circuit further comprises:

a second interconnect feature extending within the second layer and the third layer, the second interconnect feature in contact with the first interconnect feature,

wherein the implant depth profile of the impurity extends within the first interconnect feature, and does not extend within the second interconnect feature.

6 . The integrated circuit of claim 1 , wherein the impurity comprises one or more of carbon, helium, argon, or nitrogen.

7 . The integrated circuit of claim 1 , wherein:

the first layer comprises a third section, and a fourth section laterally adjacent to the third section;

the third layer comprises a fifth section above the third section of the first layer, and a sixth section above the fourth section of the first layer, the fifth section laterally adjacent to the sixth section;

the first distribution includes a higher concentration of the impurity in the third section than in the fourth section; and

the second distribution includes a higher concentration of the impurity in the sixth section than in the fifth section.

8 . The integrated circuit of claim 7 , wherein the implant depth profile of the impurity does not extend within the fifth section of the third layer.

9 . The integrated circuit of claim 7 , wherein the device is a transistor, and wherein the integrated circuit further comprises:

a memory cell comprising the transistor and a capacitor, wherein the transistor is within the third section of the first layer, and wherein the fourth section of the first layer lacks a transistor of a memory cell.

10 . The integrated circuit of claim 7 , comprising:

a memory cell comprising a transistor and a capacitor, wherein the transistor of the memory cell is within the third section of the first layer; and

a logic circuit associated with the memory cell within the fourth section of the first layer.

11 . The integrated circuit of claim 1 , comprising:

a memory cell comprising a transistor and a capacitor, wherein the transistor is within the first layer, and the capacitor is within the second layer.

12 . The integrated circuit of claim 11 , wherein the transistor is a thin film transistor.

13 . The integrated circuit of claim 11 , wherein:

the transistor is a thin film transistor comprising

a body including semiconductor material,

a gate stack below the body,

a first source or drain region above the body and coupled to a bit line of the memory cell, and

a second source or drain region above the body and coupled to an electrode of the capacitor.

14 . The integrated circuit of claim 1 , wherein:

the third layer comprises a third section above the first section of the dielectric material of the first layer, and a fourth section above the second section of the dielectric material of the first layer; and

more than 60% of the impurity within the third layer is within the fourth section of the third layer.

15 . The integrated circuit of claim 1 , wherein:

more than 60% of the impurity within the first layer is within the first section of the dielectric material of the first layer.

16 . An integrated circuit comprising:

a layer comprising dielectric material, wherein the dielectric material of the layer has a first section and a second section, the first section laterally adjacent to the second section;

an etch stop layer above the layer; and

an impurity within the first and second sections of the dielectric material of the layer and within the etch stop layer, wherein a distribution of the impurity within the first section is at a first average vertical distance from a top surface of the etch stop layer, wherein a distribution of the impurity within the second section is at a second average vertical distance from the top surface of the etch stop layer, the first average vertical distance different from the second average vertical distance.

17 . The integrated circuit of claim 16 , wherein a concentration of the impurity within the first section is different from a concentration of the impurity within the second section.

18 . The integrated circuit of claim 16 , wherein:

the etch stop layer has a third section above the first section of the dielectric material of the layer, and a fourth section above the second section of the dielectric material of the layer, the third section laterally adjacent to the fourth section; and

a concentration of the impurity within the third section of the etch stop layer is different from a concentration of the impurity within the fourth section of the etch stop layer.

19 . The integrated circuit of claim 16 , wherein the layer is a first layer, the integrated circuit comprising:

a second layer above the etch stop layer, wherein the distribution of the impurity does not extend upwards within the second layer.

20 . The integrated circuit of claim 16 , wherein more than 60% of the impurity within the layer is within the first section of the dielectric material of the layer.

21 . An integrated circuit comprising:

a first layer comprising dielectric material, and one or both of an interconnect feature and a device within the first layer;

a second layer above the first layer, the second layer comprising dielectric material; and

a third layer between the first layer and the second layer, the third layer comprising dielectric material that is different than the dielectric material of the first and second layers; and

wherein the dielectric material of the first layer comprises a first section and a second section, the first section laterally adjacent to the second section within the dielectric material of the first layer, the impurity within the first section is at a first average depth from a top surface of the third layer, and the impurity within the second section is at a second average depth from the top surface of the third layer, wherein the first average depth is more than the second average depth.

22 . The integrated circuit of claim 21 , wherein the impurity is not present in the second layer.

23 . The integrated circuit of claim 21 , wherein more than 60% of the impurity within the first layer is within the first section of the dielectric material of the first layer.