Integrated circuit device including gate contact

1 . An integrated circuit device comprising:

a substrate comprising a first device area, a second device area, and a field area including an element isolation layer and disposed between the first device area and the second device area;

active regions extending in a first direction in the first device area;

a first gate structure extending in a second direction intersecting the first direction in the first device area and the field area;

a second gate structure spaced apart from the first gate structure in the first direction;

a first gate contact disposed on the first gate structure in the first device area to vertically overlap one of the active regions in a direction perpendicular to the substrate; and

a second gate contact disposed on the second gate structure in the field area to be spaced apart from regions that vertically overlap the active regions in the direction perpendicular to the substrate,

wherein the first gate contact is disposed at a level equal to or lower than an upper end of the first gate structure,

wherein the second gate contact is disposed at a level equal to or lower than an upper end of the second gate structure,

wherein a first minimum width of the first gate contact and a second minimum width of the second gate contact are different from each other,

wherein with respect to the substrate, a first height of the first gate contact is less than a second height of the second gate contact,

wherein the first gate structure comprises a gate electrode and a gate capping layer disposed on the gate electrode, and

wherein with respect to the substrate, a height of the gate capping layer in the first device area is smaller than a height of the gate capping layer in the field area.

2 . The integrated circuit device according to claim 1 , wherein the first minimum width of the first gate contact is greater than the second minimum width of the second gate contact.

3 . The integrate circuit device according to claim 1 , wherein the first minimum width of the first gate contact is smaller than the second minimum width of the second gate contact.

4 . The integrate circuit device according to claim 1 , wherein the first gate structure has a smaller height in the first device area than in the field area.

5 . The integrated circuit device according to claim 1 , wherein, with reference to an upper surface of the substrate, a level of an uppermost end of the gate capping layer in the first device area is lower than a level of an uppermost end of the gate capping layer in the field area.

6 . The integrated circuit device according to claim 1 , further comprising:

a source/drain region disposed on the active regions between the first gate structure and the second gate structure; and

a source/drain contact disposed on the source/drain region,

wherein the source/drain contact comprises a first portion and a second portion, wherein the first portion has a first height, and the second portion has a second height greater than the first height.

7 . The integrated circuit device according to claim 6 , wherein the second portion does not overlap with the first gate contact in the first direction.

8 . The integrated circuit device according to claim 6 , further comprising:

an interlayer insulating layer disposed on the first gate structure, the second gate structure and the source/drain region; and

a buried insulating layer contacting the source/drain contact and the interlayer insulating layer.

9 . An integrated circuit device comprising:

a substrate comprising a first device area, a second device area, and a field area including an element isolation layer and disposed between the first device area and the second device area;

active regions extending in a first direction in the first device area;

a first gate electrode extending in a second direction intersecting the first direction in the first device area and the field area;

a first gate capping layer disposed on the first gate electrode;

a second gate electrode spaced apart from the first gate electrode in the first direction;

a second gate capping layer disposed on the second gate electrode;

a first gate contact overlapping the first gate electrode in the first device area, extending through the first gate capping layer in the first device area, and vertically overlapping one of the active regions in a direction perpendicular to the substrate; and

a second gate contact overlapping the second gate electrode in the field area, extending through the second gate capping layer in the field area, and being spaced apart from regions that vertically overlap the active regions in the direction perpendicular to the substrate,

wherein a first minimum width of the first gate contact and a second minimum width of the second gate contact are different from each other,

wherein with respect to the substrate, a first height of the first gate contact is less than a second height of the second gate contact,

wherein with respect to the substrate, a height of the first gate capping layer in the first device area is smaller than a height of the second gate capping layer in the field area.

10 . The integrated circuit device according to claim 9 , wherein the first minimum width of the first gate contact is greater than the second minimum width of the second gate contact.

11 . The integrate circuit device according to claim 9 , wherein the first minimum width of the first gate contact is smaller than the second minimum width of the second gate contact.

12 . The integrated circuit device according to claim 9 , wherein the active regions comprise wire patterns respectively surrounded by the first gate electrode and the second gate electrode while being spaced apart from one another.

13 . An integrated circuit device comprising:

a substrate comprising a first device area, a second device area, and a field area including an element isolation layer and disposed between the first device area and the second device area;

active regions extending in a first direction in the first device area;

a first gate electrode extending in a second direction intersecting the first direction in the first device area and the field area;

a first gate capping layer disposed on the first gate electrode;

a second gate electrode spaced apart from the first gate electrode in the first direction;

a second gate capping layer disposed on the second gate electrode;

a first gate contact connected to the first gate electrode, penetrating the first gate capping layer in the first device area, and vertically overlapping one of the active regions in a direction perpendicular to the substrate;

a second gate contact connected to the second gate electrode, penetrating the second gate capping layer in the field area, and being spaced apart from regions that vertically overlap the active regions in the direction perpendicular to the substrate;

a source/drain region disposed on the active regions; and

a source/drain contact disposed on the source/drain region,

wherein a first minimum width of the first gate contact is greater than a second minimum width of the second gate contact,

wherein with respect to the substrate, a first height of the first gate contact is less than a second height of the second gate contact, and

wherein with respect to the substrate, a height of the first gate capping layer in the first device area is smaller than a height of the second gate capping layer in the field area.

14 . The integrated circuit device according to claim 13 , wherein:

the source/drain contact comprises a first portion and a second portion, wherein the first portion has a first height, and the second portion has a second height greater than the first height.