Semiconductor structure and fabrication method thereof
A semiconductor structure includes a bottom wafer having a bottom substrate and a bottom interconnect structure on the bottom substrate, and a top wafer having a top substrate with a front surface and a rear surface and a top interconnect structure disposed on the front surface of the top substrate. The top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer. An oxide-nitride-oxide (ONO) dielectric layer covers the rear surface of the top substrate. A plurality of conductive vias is disposed on the rear surface and extending into the ONO dielectric layer and the top substrate.
1 . A semiconductor structure, comprising:
a bottom wafer comprising a bottom substrate and a bottom interconnect structure on the bottom substrate;
a top wafer having a top substrate with a front surface and a rear surface, and a top interconnect structure disposed on the front surface of the top substrate, wherein the top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer;
an oxide-nitride-oxide (ONO) dielectric layer covering the rear surface of the top substrate; and
a plurality of conductive vias disposed on the rear surface and extending into the ONO dielectric layer and the top substrate.
2 . The semiconductor structure according to claim 1 , wherein the top substrate comprises a silicon substrate and has a thickness of about 3-5 micrometers.
3 . The semiconductor structure according to claim 1 , wherein the plurality of conductive vias are electrically connected to the top interconnect structure disposed on the front surface of the top substrate.
4 . The semiconductor structure according to claim 1 , wherein the plurality of conductive vias comprise copper or aluminum.
5 . The semiconductor structure according to claim 1 , wherein the plurality of conductive vias has a top surface that are coplanar with a top surface of the ONO dielectric layer.
6 . The semiconductor structure according to claim 1 , wherein the bottom wafer has a first vertical sidewall and the top wafer has a second vertical sidewall, and wherein the first vertical sidewall is flush with the second vertical sidewall.
7 . The semiconductor structure according to claim 6 , wherein the bottom wafer has an edge portion that protrudes from the first vertical sidewall.
8 . The semiconductor structure according to claim 7 , wherein the first vertical sidewall and the second vertical sidewall are covered with a protective layer.
9 . The semiconductor structure according to claim 8 , wherein the protective layer extends onto an upper surface of the edge portion.
10 . The semiconductor structure according to claim 8 , wherein the protective layer comprises silicon oxide.
11 . A method of forming a semiconductor structure, comprising:
providing a bottom wafer comprising a bottom substrate and a bottom interconnect structure on the bottom substrate;
providing a top wafer having a top substrate with a front surface and a rear surface and a top interconnect structure disposed on the front surface of the top substrate, wherein the top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer;
forming an oxide-nitride-oxide (ONO) dielectric layer covering the rear surface of the top substrate; and
after forming the ONO dielectric layer, forming a plurality of conductive vias on the rear surface and extending into the ONO dielectric layer and the top substrate.
12 . The method according to claim 11 , wherein the top substrate comprises a silicon substrate and has a thickness of about 3-5 micrometers.
13 . The method according to claim 11 , wherein the plurality of conductive vias are electrically connected to the top interconnect structure disposed on the front surface of the top substrate.
14 . The method according to claim 11 , wherein the plurality of conductive vias comprise copper or aluminum.
15 . The method according to claim 11 , wherein the plurality of conductive vias have a top surface that is coplanar with a top surface of the ONO dielectric layer.
16 . The method according to claim 11 , wherein the bottom wafer has a first vertical sidewall and the top wafer has a second vertical sidewall, and wherein the first vertical sidewall is flush with the second vertical sidewall.
17 . The method according to claim 16 , wherein the bottom wafer has an edge portion that protrudes from the first vertical sidewall.
18 . The method according to claim 17 , wherein the first vertical sidewall and the second vertical sidewall are covered with a protective layer.
19 . The method according to claim 18 , wherein the protective layer extends onto an upper surface of the edge portion.
20 . The method according to claim 18 , wherein the protective layer comprises silicon oxide.