Semiconductor structure and method for forming the same
A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.
1 . A method for forming a semiconductor structure, comprising:
forming an isolation structure surrounding a first active region;
forming a first dummy gate structure across the first active region and the isolation structure;
replacing at least a portion of the first dummy gate structure with an insulating strip;
forming a first cutting feature through the insulating strip and the isolation structure;
forming a first contact rail in the first cutting feature;
forming a first via rail in the first cutting feature and overlapping the first contact rail; and
forming a first metal line overlapping the first via rail.
2 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising:
forming a second cutting feature through the insulating strip and the isolation structure, wherein the first active region is located between the first cutting feature and the second cutting feature, and the insulating strip continuously extends from the first cutting feature to the second cutting feature.
3 . The method for forming the semiconductor structure as claimed in claim 2 , further comprising:
forming a second contact rail in the second cutting feature;
forming a second via rail in the second cutting feature and overlapping the second contact rail; and
forming a second metal line overlapping the second via rail.
4 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising, after forming the first contact rail in the first cutting feature and before forming the first via rail in the first cutting feature and overlapping the first contact rail:
polishing the first active region and the isolation structure to expose a surface of the first cutting feature from backside.
5 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising:
forming a second metal line over the first contact rail and electrically connected to the first metal line, wherein the first contact rail and the first via rail are vertically sandwiched between the first metal line and the second metal line.
6 . The method for forming the semiconductor structure as claimed in claim 1 , wherein replacing at least the portion of the first dummy gate structure with the insulating strip comprises:
etching the first dummy gate structure, the first active region and the isolation structure to form a trench; and
forming a dielectric material in the trench.
7 . The method for forming the semiconductor structure as claimed in claim 1 , wherein forming the first via rail in the first cutting feature and overlapping the first contact rail comprises:
etching the first cutting feature to form a trench exposing a surface of the first contact rail; and
filling the trench with a conductive material.
8 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising:
forming a second dummy gate structure across the first active region and the isolation structure; and
replacing the second dummy gate structure with a gate stack, wherein the gate stack includes a gate dielectric layer over the first active region and a metal gate electrode layer over the gate dielectric layer.
9 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising:
forming the isolation structure surrounding a second active region;
forming a source/drain feature over the second active region, wherein the first metal line is electrically connected to the source/drain feature; and
forming a gate stack across the second active region and the isolation structure.
10 . The method for forming the semiconductor structure as claimed in claim 9 , wherein the second active region is narrower than the first active region.
11 . A method for forming a semiconductor structure, comprising:
forming a plurality of active regions over a substrate;
forming a plurality of insulating strips across the plurality of active regions, wherein the plurality of insulating strips vertically extend through the active regions and into the substrate;
forming a first contact rail between a first active region and a second active region in the plurality of active regions and forming a second contact rail between the second active region and a third active region in the plurality of active regions; and
forming a first via rail and a second via rail on the first contact rail and the second contact rail, respectively.
12 . The method for forming the semiconductor structure as claimed in claim 11 , further comprising:
forming a cutting feature between the second active region and a fourth active region in the plurality of active regions, wherein the first active region is formed in a first p-type well, and the second active region and the fourth active region are formed in a second p-type well, and the third active region is formed in a third p-type well between the first p-type well and the second p-type well.
13 . The method for forming the semiconductor structure as claimed in claim 12 , further comprising:
forming a third via rail in the cutting feature;
forming a first Vdd power rail on the first via rail;
forming a second Vdd power rail on the second via rail; and
forming a Vss power rail on the third via rail.
14 . The method for forming the semiconductor structure as claimed in claim 11 , further comprising:
forming a stack of alternating first semiconductor layers and second semiconductor layers over the substrate;
patterning the stack and a portion of the substrate to form the plurality of active regions;
removing the first semiconductor layers to form a plurality of nanostructures from the second semiconductor layers; and
forming a gate stack surrounding the plurality of nanostructures.
15 . A method for forming a semiconductor structure, comprising:
forming an isolation structure surrounding each of a first active region and a second active region and isolating the second active region from the first active region, the second active region being narrower than the first active region;
forming a first dummy gate structure across the first active region and the isolation structure;
etching the first dummy gate structure, the first active region and the isolation structure to form a trench; and
forming a dielectric material in the trench to form an insulating strip;
forming a first cutting feature through the insulating strip and the isolation structure;
forming a first contact rail in the first cutting feature;
forming a first via rail in the first cutting feature and overlapping the first contact rail; and
forming a first metal line overlapping the first via rail.
16 . The method for forming the semiconductor structure as claimed in claim 15 , further comprising:
forming a second dummy gate structure across the first active region and the isolation structure;
replacing the second dummy gate structure with a gate stack, wherein the gate stack includes a gate dielectric layer over the first active region and a metal gate electrode layer over the gate dielectric layer; and
forming a second cutting feature through the insulating strip and the isolation structure, wherein the first active region is located between the first cutting feature and the second cutting feature, and the insulating strip continuously extends from the first cutting feature to the second cutting feature.
17 . The method for forming the semiconductor structure as claimed in claim 16 , further comprising:
forming a second contact rail in the second cutting feature;
forming a second via rail in the second cutting feature and overlapping the second contact rail; and
forming a second metal line overlapping the second via rail.
18 . The method for forming the semiconductor structure as claimed in claim 15 , further comprising, after forming the first contact rail in the first cutting feature and before forming the first via rail in the first cutting feature and overlapping the first contact rail:
polishing the first active region and the isolation structure to expose a surface of the first cutting feature from backside.
19 . The method for forming the semiconductor structure as claimed in claim 15 , further comprising:
forming a second metal line over the first contact rail and electrically connected to the first metal line, wherein the first contact rail and the first via rail are vertically sandwiched between the first metal line and the second metal line.
20 . The method for forming the semiconductor structure as claimed in claim 15 , wherein forming the first via rail in the first cutting feature and overlapping the first contact rail comprises:
etching the first cutting feature to form a trench exposing a surface of the first contact rail; and
filling the trench with a conductive material.