Semiconductor devices with active regions and conductive regions of two widths and methods of designing and manufacturing the same

1 . A semiconductor device, comprising:

a first conductive region having a first width and extending along a first direction;

a second conductive region having a second width and extending along the first direction, the first width greater than the second width;

a first active region having a third width and extending along the first direction;

a second active region having a fourth width and extending along the first direction, the third width less than the fourth width; and

a third conductive region extending along a second direction and electrically connected to the first conductive region through a via, the second direction different from the first direction,

wherein the first and second active regions are neighboring active regions.

2 . The semiconductor device of claim 1 , wherein:

the first conductive region is in a first layer;

the third conductive region is in a second layer; and

the second direction is perpendicular to the first direction.

3 . The semiconductor device of claim 2 ,

wherein the via is coupled between the first conductive region and the third conductive region, the via having a fifth width equal to or less than the first width.

4 . The semiconductor device of claim 1 , further comprising:

a third active region having the fourth width, extending along the first direction, and coupled to the first active region.

5 . The semiconductor device of claim 1 , wherein a space between the third conductive region and the first active region is equal to or greater than a threshold of space.

6 . The semiconductor device of claim 1 , further comprising:

a fourth conductive region having the second width and extending along the first direction;

wherein:

the first, second, and fourth conductive regions are in a first layer; and

the third conductive region is in a second layer and extends along the second direction perpendicular to the first direction.

7 . The semiconductor device of claim 1 , further comprising:

a fourth conductive region extending along the second direction; and

an isolating region extending along the second direction and formed between the third and fourth conductive regions.

8 . The semiconductor device of claim 7 , wherein:

the first and second active regions are in a first layer;

the third and fourth conductive regions and the isolating region are in a second layer, the second layer different from the first layer;

the third conductive region extends in the second layer and above the second active region in the first layer; and

the fourth conductive region extends in the second layer and above the first active region in the first layer.

9 . The semiconductor device of claim 7 , wherein the isolating region is a first isolating region, the semiconductor device further comprising:

a second isolating region extending along the second direction,

wherein:

the first and second isolating regions are on opposite sides of the first active region; and

a distance between the first and second isolating regions is equal to or greater than a threshold distance.

10 . The semiconductor device of claim 1 , wherein:

the via is a first via coupled between the first conductive region and the third conductive region; and

the semiconductor device further comprises a second via coupled to a source of a transistor,

wherein the first and second vias are on opposite sides of the first active region.

11 . The semiconductor device of claim 1 , further comprising:

a fourth conductive region having the first width and extending along the first direction;

a fifth conductive region having the second width and extending along the first direction;

a third active region having the third width and extending along the first direction;

a fourth active region having the fourth width and extending along the first direction; and

a sixth conductive region extending along the second direction and electrically connected to the fourth conductive region,

wherein the third and fourth active regions are neighboring active regions.

12 . The semiconductor device of claim 11 , wherein:

the third and sixth conductive regions are on opposite sides of the first active region; and

the third and sixth conductive regions are on opposite sides of the third active region.

13 . The semiconductor device of claim 11 , wherein:

the via is a first via coupled between the first conductive region and the third conductive region; and

the semiconductor device further comprises:

a second via coupled between the fourth conductive region and the sixth conductive region; and

a third via coupled to a source of a transistor;

wherein the second and third vias are on opposite sides of the third active region.

14 . The semiconductor device of claim 13 , wherein the transistor is a first transistor, the semiconductor device further comprising:

a fourth via coupled to a source of a second transistor,

wherein the first and fourth vias are on opposite sides of the first active region.

15 . A flip-flop circuit, comprising:

a first conductive region having a first width and extending along a first direction;

a second conductive region having a second width and extending along the first direction, the first width greater than the second width;

an active region having a third width and a fourth width, and extending along the first direction, the third width less than the fourth width; and

a third conductive region extending along a second direction and electrically connected to the first conductive region, the second direction different from the first direction.

16 . The flip-flop circuit of claim 15 , wherein:

the first, second, and third conductive regions and the active region are a first plurality of circuits; and

the flip-flop circuit further comprises a second plurality of circuits comprising a longest circuit path of the flip-flop circuit.

17 . The flip-flop circuit of claim 15 , further comprising:

a multiplexer comprising a data input circuit and a scan input circuit,

wherein the scan input circuit comprises at least a part of the active region.

18 . A semiconductor device, comprising a plurality of circuit cells, wherein at least one of the plurality of circuit cells includes:

a first active region having a first width and extending along a first direction in a first layer;

a second active region having the first width and a second width and extending along the first direction in the first layer, wherein the second width is less than the first width, and the first and second active regions are neighboring active regions;

a first conductive region having a third width and extending along the first direction in a second layer, the second layer being above the first layer;

a second conductive region having a fourth width and extending along the first direction in the second layer, the third width being greater than the fourth width; and

a third conductive region extending along a second direction in a third layer and electrically connected to the first conductive region through a via, the second direction being different from the first direction, the third layer being between the first and second layers.

19 . The semiconductor device of claim 18 , wherein the at least one of the plurality of circuit cells further includes:

third and fourth active regions having the first width and extending along the first direction in the first layer.

20 . The semiconductor device of claim 18 , wherein the third conductive region extends along the second direction, above and across the first active region, and toward a portion of the second active region in a plan view, the portion of the second active region having the second width.