Integration of via and bottom electrode for memory cell

1 . A method of forming an integrated chip, comprising:

forming a first wire level over a substrate;

depositing an etch stop layer over the first wire level;

etching the etch stop layer to form an opening over the first wire level;

depositing a barrier layer over the etch stop layer, the barrier layer extending into the opening;

depositing a first conductive layer over the barrier layer and in the opening;

performing a planarization into the first conductive layer to flatten a top of the first conductive layer, wherein the planarization stops before reaching the barrier layer;

depositing a data storage layer and a second conductive layer over the first conductive layer; and

patterning the barrier layer, the first conductive layer, the data storage layer, and the second conductive layer to form a memory cell at the opening.

2 . The method of claim 1 , wherein patterning the first conductive layer, the data storage layer, and the second conductive layer comprises:

patterning the second conductive layer into a top electrode using a first etching process;

forming a spacer surrounding the top electrode; and

patterning the data storage layer and the first conductive layer into a data storage structure and a conductive structure using a second etching process.

3 . The method of claim 2 , wherein the data storage structure, the conductive structure, and the barrier layer form a common sidewall extending from the etch stop layer to a top surface of the data storage structure.

4 . The method of claim 2 , wherein the conductive structure has a first width and the top electrode has a second width that is less than the first width.

5 . The method of claim 2 , further comprising:

depositing a dielectric layer surrounding the memory cell; and

forming a first via extending through the dielectric layer, from over the memory cell to the top electrode.

6 . The method of claim 5 , further comprising:

forming a second via extending from an elevation level with a top of the first via to an elevation level with a top of the first wire level; and

forming a second wire level electrically coupled to the first via and the second via.

7 . The method of claim 2 , wherein a first portion of the first conductive layer is demarcated by the opening in the etch stop layer, the first portion being configured to function as a bottom via, and wherein the patterning of the first conductive layer into the conductive structure defines a bottom electrode in a second portion of the conductive structure overlying the first portion.

8 . A method of forming an integrated chip, comprising:

depositing an etch stop layer over a first region and a second region of a substrate;

performing an etching process to define an opening in the etch stop layer in the first region;

depositing a barrier layer over the etch stop layer and extending into the opening;

depositing a first conductive layer over the etch stop layer, the first conductive layer having a protrusion demarcated by the opening in the etch stop layer with a first width;

depositing a ferroelectric film over the first conductive layer;

depositing a second conductive layer over the ferroelectric film; and

patterning the first conductive layer, the ferroelectric film, the second conductive layer, and the barrier layer, the patterning defining a patterned barrier layer and a pad of the first conductive layer directly over the protrusion and the etch stop layer, the pad having a second width greater than the first width and substantially equal to a width of the patterned barrier layer.

9 . The method of claim 8 , wherein the deposition of the first conductive layer is performed using a first deposition step, and wherein the protrusion and the pad of the first conductive layer are deposited during the first deposition step.

10 . The method of claim 8 , further comprising performing a planarization process, resulting in the first conductive layer having a planarized surface extending directly over the protrusion and the etch stop layer.

11 . The method of claim 10 , wherein after patterning the first conductive layer, the pad extends from a first edge of the planarized surface to a second edge of the planarized surface opposite the first edge, and the first and second edges are spaced from and on opposite sides of the opening.

12 . The method of claim 8 , wherein the pad and the protrusion of the first conductive layer form a “T” shape when viewed from a cross-sectional view, and wherein the barrier layer extends along bottom surfaces of the “T” shape.

13 . The method of claim 8 , wherein patterning the first conductive layer, the ferroelectric film, the second conductive layer, and the barrier layer further comprises:

patterning the second conductive layer using a first etching process;

patterning the first conductive layer using a second etching process different from the first etching process; and

patterning the ferroelectric film during the same etching process as the patterning of the first conductive layer.

14 . The method of claim 13 , wherein patterning the first conductive layer, the ferroelectric film, and the second conductive layer forms a plurality of ferroelectric tunnel junction cells that are confined to the first region.

15 . A method of forming an integrated chip, comprising:

patterning an etch stop layer over a substrate to form an opening extending through the etch stop layer;

depositing a barrier layer over the etch stop layer, the barrier layer lining sidewalls of the etch stop layer surrounding the opening;

depositing a first conductive layer over the barrier layer, filling the opening;

depositing a data storage layer and a second conductive layer over the first conductive layer; and

patterning the second conductive layer into a top electrode;

forming a spacer surrounding sidewalls of the top electrode;

patterning the data storage layer, the first conductive layer, and the barrier layer to form a memory cell; and

forming a second etch stop layer extending over the memory cell, the second etch stop layer covering sidewalls of remaining portions of the data storage layer and the first conductive layer; and

forming a second barrier layer over the second etch stop layer, wherein the second barrier layer comprises a different material from the second etch stop layer and is separated from the memory cell by the second etch stop layer.

16 . The method of claim 15 , further comprising forming a first wire over the substrate before patterning the etch stop layer, wherein the opening formed by patterning the etch stop layer exposes the first wire.

17 . The method of claim 15 , wherein the barrier layer comprises a conductive material and extends from a bottom of the sidewalls of the etch stop layer to over an upper surface of the etch stop layer.

18 . The method of claim 15 , wherein the first conductive layer extends across an upper surface of the etch stop layer, and wherein the barrier layer separates the first conductive layer from the etch stop layer.

19 . The method of claim 15 , further comprising:

forming a masking layer over the top electrode before patterning the data storage layer, the first conductive layer, and the barrier layer; and

removing the masking layer after the data storage layer, the first conductive layer, and the barrier layer are patterned.

20 . The method of claim 15 , wherein the first conductive layer has an upper surface spaced from a top surface of the barrier layer in a vertical direction.