Metal routing that overlaps NMOS and PMOS regions of a transistor
Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.
1 . A circuit structure comprising:
a PMOS region in a first plane;
an NMOS region in the first plane, wherein the PMOS region and the NMOS region are substantially parallel to each other and are separated from each other by a separation region;
an electrical routing track in a second plane above a level of the first plane and substantially parallel with the first plane; and
wherein a width of a portion of the electrical routing track is directly above and overlaps the separation region, wherein a first side of the width is directly above a portion of the PMOS region, wherein a second side of the width opposite the first side is directly above a portion of the NMOS region, and wherein the electrical routing track has a longest dimension parallel with a longest dimension of the separation region.
2 . The circuit structure of claim 1 , wherein the electrical routing track is electrically coupled with the PMOS region and the NMOS region.
3 . The circuit structure of claim 1 , wherein the electrical routing track is substantially parallel with the PMOS region and the NMOS region.
4 . The circuit structure of claim 1 , wherein the electrical routing track is a metal routing within a metal 0 layer of the circuit structure.
5 . The circuit structure of claim 1 , wherein the electrical routing track is a first electrical routing track, and further comprising:
a second electrical routing track in the second plane, the second electrical routing track on a first side of the first electrical routing track and above the PMOS region; and
a third electrical routing track in the second plane, the third electrical routing track on a second side of the first electrical routing track opposite the first side of the electrical routing track, wherein the third electrical routing track is above the NMOS region.
6 . The circuit structure of claim 5 , wherein the first electrical routing track has a first width, the second electrical routing track has a second width, and the third electrical routing track has a third width; and
wherein the first width is greater than the second width or the third width.
7 . The circuit structure of claim 5 , wherein the first electrical routing track, the second electrical routing track, and the third electrical routing track are electrically isolated from each other within the circuit structure.
8 . The circuit structure of claim 5 , wherein the second electrical routing track and the third electrical routing track are metal routings within a metal 0 layer of the circuit structure.
9 . The circuit structure of claim 1 , wherein the electrical routing track further includes a first segment and a second segment, and wherein the first segment and the second segment are electrically isolated from each other.
10 . The circuit structure of claim 1 , further comprising:
a first feature on the NMOS region;
a second feature on the PMOS region; and
wherein the electrical routing track electrically couples the first feature with the second feature.
11 . The circuit structure of claim 10 , wherein the first feature and second feature include diffusion contacts.
12 . The circuit structure of claim 10 , further comprising:
a first via that extends from a portion of the electrical routing track directly above the NMOS region to the first feature on the NMOS region; and
a second via that extends from a portion of the electrical routing track directly above the PMOS region to the second feature on the PMOS region.
13 . The circuit structure of claim 12 , wherein the first via and the second via are filled with a metal that is electrically conductive.
14 . A system comprising:
an electrical component; and
a circuit structure electrically coupled with the component, the circuit structure including:
a PMOS region in a first plane;
an NMOS region in the first plane, wherein the PMOS region and the NMOS region are substantially parallel to each other and are separated from each other by a separation region;
a first metal routing in a second plane that is above the first plane and parallel to the first plane, wherein the first metal routing is directly above the separation region and wherein a width of the first metal routing overlaps the separation region, wherein a first side of the first metal routing is directly above a portion of the PMOS region, wherein a second side of the first metal routing opposite the first side of the first metal routing is directly above a portion of the NMOS region, and wherein the first metal routing has a longest dimension parallel with a longest dimension of the separation region; and
a second metal routing in the second plane on a side of the first metal routing, wherein the second metal routing is directly above either the PMOS region or the NMOS region.
15 . The system of claim 14 , wherein the first metal routing and the second metal routing are in a metal 0 layer.
16 . The system of claim 14 , wherein the electrical component is a portion of a memory structure.
17 . The system of claim 14 , wherein the first metal routing and the second metal routing are electrically isolated from each other.
18 . A circuit structure comprising:
a PMOS region in a first plane;
an NMOS region in the first plane, wherein the PMOS region and the NMOS region are substantially parallel to each other and are separated from each other by a separation region;
a first electrical routing track in a second plane above a level of the first plane and substantially parallel with the first plane;
wherein a width of a portion of the first electrical routing track is directly above and overlaps the separation region, wherein a first side of the width is directly above a portion of the PMOS region, and wherein a second side of the width opposite the first side is directly above a portion of the NMOS region;
a second electrical routing track in the second plane, the second electrical routing track on a first side of the first electrical routing track and above the PMOS region; and
a third electrical routing track in the second plane, the third electrical routing track on a second side of the first electrical routing track opposite the first side of the electrical routing track, wherein the third electrical routing track is above the NMOS region, and wherein the first electrical routing track has a longest dimension parallel with a longest dimension of the second electrical routing track and with a longest dimension of the third electrical routing track.
19 . The circuit structure of claim 18 , wherein the first electrical routing track has a first width, the second electrical routing track has a second width, and the third electrical routing track has a third width; and
wherein the first width is greater than the second width or the third width.
20 . The circuit structure of claim 18 , wherein the first electrical routing track, the second electrical routing track, and the third electrical routing track are electrically isolated from each other within the circuit structure.
21 . The circuit structure of claim 18 , wherein the second electrical routing track and the third electrical routing track are metal routings within a metal 0 layer of the circuit structure.
22 . A circuit structure comprising:
a PMOS region in a first plane;
an NMOS region in the first plane, wherein the PMOS region and the NMOS region are substantially parallel to each other and are separated from each other by a separation region;
an electrical routing track in a second plane above a level of the first plane and substantially parallel with the first plane; and
wherein a width of a portion of the electrical routing track is directly above and overlaps the separation region, wherein a first side of the width is directly above a portion of the PMOS region, wherein a second side of the width opposite the first side is directly above a portion of the NMOS region, and wherein the electrical routing track further includes a first segment and a second segment, wherein the first segment and the second segment are electrically isolated from each other, and wherein the electrical routing track has a longest dimension parallel with a longest dimension of the first segment and with a longest dimension of the second segment.