Three-dimensional memory devices and methods for forming the same
In certain aspects, a three-dimensional (3D) memory device includes a stack structure, and a slit structure extending. The stack structure includes interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure. Each one of the conductive layers has a thickened portion in the staircase structure. The thickened portion extends along a first direction. The slit structure extends through the stack structure and along a second direction perpendicular to the first direction, such that the slit structure cuts off at least one, but not all, of the thickened portions of the conductive layers.
1 . A three-dimensional (3D) memory device, comprising:
a stack structure comprising interleaved conductive layers and dielectric layers, wherein edges of the interleaved conductive layers and dielectric layers define a staircase structure, and each one of the conductive layers has a thickened portion in the staircase structure, the thickened portion extending along a first direction; and
a slit structure extending through the stack structure and along a second direction perpendicular to the first direction, such that the slit structure cuts off a portion of more than one, but not all, of the thickened portions of the conductive layers,
wherein the slit structure comprises a dielectric layer; and
wherein the interleaved conductive layers and dielectric layers stacked along a third direction perpendicular to the first direction and the second direction.
2 . The 3D memory device of claim 1 , wherein
at least the thickened portion of a first conductive layer of the conductive layers is continuous along the first direction and spaced apart from the slit structure in the second direction; and
a portion of at least the thickened portion of a second conductive layer of the conductive layers is discontinuous along the first direction and cut off by the slit structure from the second direction.
3 . The 3D memory device of claim 2 , further comprising a channel structure extending through the stack structure, wherein the first conductive layer is closer to a source end of the channel structure than the second conductive layer.
4 . The 3D memory device of claim 3 , wherein the first conductive layer comprises a gate-induced-drain-leakage (GIDL) line, and the second conductive layer comprises a select gate line electrically disconnected from the GIDL line.
5 . The 3D memory device of claim 3 , further comprising a semiconductor layer in contact with the channel structure, wherein the first conductive layer is closer to the semiconductor layer than the second conductive layer.
6 . The 3D memory device of claim 5 , wherein the semiconductor layer comprises N-type doped polysilicon.
7 . The 3D memory device of claim 2 , wherein a dimension of the first conductive layer in the second direction is greater than a dimension of the second conductive layer in the second direction.
8 . The 3D memory device of claim 2 , further comprising a cut structure extending through the first conductive layer.
9 . The 3D memory device of claim 8 , wherein the cut structure stops at the thickened portion of the first conductive layer.
10 . The 3D memory device of claim 1 , wherein the thickened portions of the conductive layers comprise a metal.
11 . A three-dimensional (3D) memory device, comprising:
a semiconductor layer;
a stack structure comprising interleaved conductive layers and dielectric layers, wherein edges of the interleaved conductive layers and dielectric layers define a staircase structure, and each one of the conductive layers has a thickened portion in the staircase structure, the thickened portion extending along a first direction;
a channel structure extending through the stack structure and in contact with the semiconductor layer; and
a slit structure extending through the stack structure and along a second direction perpendicular to the first direction,
wherein the slit structure comprises a dielectric layer;
at least the thickened portion of a first conductive layer of the conductive layers is continuous along the first direction;
at least the thickened portion of a second conductive layer of the conductive layers is discontinuous along the first direction, the first conductive layer being closer to the semiconductor layer than the second conductive layer;
the slit structure cuts off a portion of more than one of the thickened portions of the conductive layers; and
the interleaved conductive layers and dielectric layers stacked along a third direction perpendicular to the first direction and the second direction.
12 . The 3D memory device of claim 11 , wherein the slit structure cuts off a portion of the thickened portion of the second conductive layer from the second direction and is spaced away from the thickened portion of the first conductive layer in the second direction.
13 . The 3D memory device of claim 1 , wherein the slit structure is electrically insulated from the conductive layers.
14 . The 3D memory device of claim 1 , wherein the slit structure comprises only the dielectric layer without a conductive contact.
15 . The 3D memory device of claim 11 , wherein the slit structure is electrically insulated from the conductive layers.
16 . The 3D memory device of claim 11 , wherein the slit structure comprises only the dielectric layer without a conductive contact.