Incorporation of superlattice semi-metals for scaled interconnects
Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD). and an interconnect over the ILD. In an embodiment, the interconnect comprises a plurality of first layers, where the first layers comprise a metal, and a plurality of second layer in an alternating pattern with the plurality of first layers. In an embodiment, the second layers comprise a two-dimensional (2D) material.
1 . An integrated circuit structure, comprising:
an interlayer dielectric (ILD); and
an interconnect over the ILD, wherein the interconnect comprises:
a plurality of first layers, wherein each of the first layers comprise a metal;
a plurality of second layers, wherein each of the second layers comprise a two-dimensional (2D) material, wherein the 2D material is a transition metal dichalcogenide (TMD), and wherein first layers and second layers are stacked over each other in an alternating pattern.
2 . The integrated circuit structure of claim 1 , wherein the first layers comprise a transition metal, and wherein the TMD comprises the transition metal.
3 . The integrated circuit structure of claim 1 , wherein sidewalls of the interconnect are vertical.
4 . The integrated circuit structure of claim 1 , wherein sidewalls of the interconnect are tapered.
5 . The integrated circuit structure of claim 4 , wherein a top surface of the interconnect is wider than a bottom surface of the interconnect.
6 . The integrated circuit structure of claim 4 , wherein a top surface of the interconnect is narrower than a bottom surface of the interconnect.
7 . The integrated circuit structure of claim 1 , wherein the plurality of second layers comprises three or more second layers.
8 . The integrated circuit structure of claim 1 , wherein the plurality of first layers each have a first thickness, and wherein the plurality of second layers each have a second thickness that is less than the first thickness.
9 . The integrated circuit structure of claim 8 , wherein the first thickness is between approximately 1 nm and approximately 50 nm, and wherein the second thickness is approximately 2 nm or less.
10 . The integrated circuit structure of claim 1 , wherein the plurality of second layers comprises at least a second layer with a first material composition and a second layer with a second material composition that is different than the first material composition.
11 . An integrated circuit structure, comprising:
an interlayer dielectric (ILD); and
an interconnect over the ILD, wherein the interconnect comprises:
a plurality of first layers, wherein each of the first layers comprise a metal;
a plurality of second layers, wherein each of the second layers comprise a two-dimensional (2D) material, and wherein first layers and second layers are stacked over each other in an alternating pattern, wherein the plurality of second layers comprises at least a second layer with a first material composition and a second layer with a second material composition that is different than the first material composition.
12 . The integrated circuit structure of claim 11 , wherein the 2D material is a semi-metal.
13 . The integrated circuit structure of claim 11 , wherein the 2D material is a transition metal dichalcogenide (TMD), and wherein the first layers comprise a transition metal, and wherein the TMD comprises the transition metal.
14 . The integrated circuit structure of claim 11 , wherein sidewalls of the interconnect are vertical.
15 . The integrated circuit structure of claim 11 , wherein sidewalls of the interconnect are tapered.
16 . The integrated circuit structure of claim 15 , wherein a top surface of the interconnect is wider than a bottom surface of the interconnect.
17 . The integrated circuit structure of claim 15 , wherein a top surface of the interconnect is narrower than a bottom surface of the interconnect.
18 . The integrated circuit structure of claim 11 , wherein the plurality of second layers comprises three or more second layers.
19 . The integrated circuit structure of claim 11 , wherein the plurality of first layers each have a first thickness, and wherein the plurality of second layers each have a second thickness that is less than the first thickness.
20 . The integrated circuit structure of claim 19 , wherein the first thickness is between approximately 1 nm and approximately 50 nm, and wherein the second thickness is approximately 2 nm or less.