Anti-fuse cells with backside power rails
View Patent ↗A device includes a memory cell including a first transistor and a second transistor disposed on a frontside of a substrate, the substrate having a first area and a second area. The memory device includes a first interconnect structure disposed on a backside of the substrate. One S/D terminal of the first transistor is coupled to one S/D terminal of the second transistor, with the other S/D terminal of the second transistor coupled to the first interconnect structure through a first via structure in the first area. The memory device includes second via structures and a third via structure both disposed in the second area and each coupled to the first interconnect structure. The first via structure and the second via structures each have a cross-sectional area that is different from that of the third via structure.
1 . A device, comprising:
a memory cell including a first transistor and a second transistor both disposed on a first side of a substrate;
a first interconnect structure disposed on a second side of the substrate opposite to the first side, wherein a first source/drain terminal of the first transistor is floating, a second source/drain terminal of the first transistor is coupled to a first source/drain terminal of the second transistor, with a second source/drain terminal of the second transistor coupled to the first interconnect structure;
a first via structure disposed in a first area of the substrate and configured to couple the second source/drain terminal of the second transistor to the first interconnect structure;
a plurality of second via structures disposed in a second area of the substrate and each coupled to the first interconnect structure; and
a third via structure disposed in the second area of the substrate and coupled to the first interconnect structure,
wherein the first via structure and the second via structures each have a first cross-sectional area, and the third via structure has a second cross-sectional area that is different from the first cross-sectional area.
2 . The device of claim 1 , wherein the first interconnect structure operatively serves as a bit line for the memory cell.
3 . The device of claim 1 , wherein a conduction path is formed by applying a programming voltage on a gate terminal of the first transistor.
4 . The device of claim 3 , wherein the conduction path extends from the gate terminal of the first transistor, through at least the second source/drain terminal of the first transistor, the first and the second source/drain terminals of the second transistor, and to the first interconnect structure.
5 . The device of claim 1 , wherein the first via structure, the second via structures, and the third via structure are coupled in parallel with one another.
6 . The device of claim 1 , wherein the first cross-sectional area is less than the second cross-sectional area.
7 . The device of claim 1 , further comprising a second interconnect structure disposed on the first side, wherein the first via structure, the second via structures, and the third via structure are respectively coupled to the second interconnect structure.
8 . The device of claim 1 , wherein at least a portion of the second area extends adjacent to the first area.
9 . The device of claim 1 , wherein the memory cell is disposed in the first area, the device further comprising a plurality of third transistors disposed in the second area, wherein a gate terminal and source/drain terminals of each of the third transistors are coupled to the first interconnect structure.
10 . The device of claim 7 , further comprising at least one fourth via structure coupling the first interconnect structure to the second interconnect structure in the first area.
11 . The device of claim 1 , further comprising a third transistor, wherein the second via structures couple both source/drain regions of the third transistor to a second interconnect structure.
12 . A device, comprising:
a memory cell including a first transistor and a second transistor both disposed a substrate;
a first interconnect structure disposed on the substrate, wherein a first source/drain terminal of the first transistor is floating, a second source/drain terminal of the first transistor is coupled to a first source/drain terminal of the second transistor, with a second source/drain terminal of the second transistor coupled to the first interconnect structure;
a first via structure disposed in a first area of the substrate and configured to couple the second source/drain terminal of the second transistor to the first interconnect structure;
a plurality of second via structures disposed in a second area of the substrate and each coupled to the first interconnect structure; and
a third via structure disposed in the second area of the substrate and coupled to the first interconnect structure,
wherein the first via structure and the second via structures each have a first resistance, and the third via structure has a second resistance that is lower than the first resistance.
13 . The device of claim 12 , wherein the first interconnect structure operatively serves as a bit line for the memory cell.
14 . The device of claim 12 , wherein a conduction path is formed by applying a programming voltage on a gate terminal of the first transistor.
15 . The device of claim 14 , wherein the conduction path extends from the gate terminal of the first transistor, through at least the second source/drain terminal of the first transistor, the first and the second source/drain terminals of the second transistor, and to the first interconnect structure.
16 . The device of claim 12 , wherein the first via structure, the second via structures, and the third via structure are coupled in parallel with one another.
17 . The device of claim 12 , wherein the first via structure and the second via structures each have a first cross-sectional area, and the third via structure has a second cross-sectional area that is different from the first cross-sectional area, and wherein the first cross-sectional area is less than the second cross-sectional area.
18 . The device of claim 12 , further comprising a second interconnect structure disposed on the substrate, wherein the first via structure, the second via structures, and the third via structure are respectively coupled to the second interconnect structure.
19 . The device of claim 12 , wherein at least a portion of the second area extends adjacent to the first area.
20 . The device of claim 12 , wherein the memory cell is disposed in the first area, the device further comprising a plurality of third transistors disposed in the second area, wherein a gate terminal and source/drain terminals of each of the third transistors are coupled to the first interconnect structure.