IC package with dummy die heat spreader
According to embodiments of the present disclosure, a semiconductor package is provided and may include: a substrate; a semiconductor chip on the substrate; a dummy chip on the semiconductor chip; and a first protection layer between the semiconductor chip and the dummy chip. The dummy chip may include: a semiconductor substrate including a first surface and a second surface, opposite to the first surface, the first surface being closer than the second surface to the semiconductor chip; a second protection layer on the first surface; and at least one penetration electrode penetrating the semiconductor substrate and the second protection layer. The at least one penetration electrode may be spaced apart from the semiconductor chip in a first direction perpendicular to a top surface of the semiconductor chip, and the first protection layer may be in contact with the second protection layer.
1 . A semiconductor package, comprising:
a substrate;
a semiconductor chip on the substrate;
a dummy chip on the semiconductor chip; and
a first protection layer between the semiconductor chip and the dummy chip,
wherein the dummy chip comprises:
a semiconductor substrate comprising a first surface and a second surface, opposite to the first surface, the first surface being closer than the second surface to the semiconductor chip;
a second protection layer on the first surface; and
at least one penetration electrode penetrating the semiconductor substrate and the second protection layer,
wherein the at least one penetration electrode is spaced apart from the semiconductor chip in a first direction perpendicular to a top surface of the semiconductor chip, and
wherein the first protection layer is in contact with the second protection layer.
2 . The semiconductor package of claim 1 , wherein the semiconductor chip is a logic chip.
3 . The semiconductor package of claim 1 , wherein the at least one penetration electrode is in contact with a top surface of the first protection layer.
4 . The semiconductor package of claim 1 , wherein the first protection layer and the second protection layer comprise at least one from among SiO 2 , SiN, SiCN, and SiCO.
5 . The semiconductor package of claim 1 , wherein a thickness of the second protection layer is in a range from 0.2 μm to 1 μm.
6 . The semiconductor package of claim 1 , wherein the semiconductor chip comprises a semiconductor substrate and an interconnection layer on the semiconductor substrate of the semiconductor chip, and
the first protection layer is in contact with the semiconductor substrate of the semiconductor chip.
7 . The semiconductor package of claim 1 , wherein the dummy chip further comprises a barrier metal on the at least one penetration electrode, and
the barrier metal comprises at least one from among titanium (Ti), titanium nitride (TiN), and tungsten (W).
8 . The semiconductor package of claim 7 , wherein the dummy chip further comprises a liner between the barrier metal and the semiconductor substrate, and
the liner comprises at least one from among silicon oxide (SiO 2 ) silicon nitride (SiN), silicon carbon nitride (SiCN), and silicon carboxide (SiCO).
9 . The semiconductor package of claim 1 , wherein a level of a top surface of the at least one penetration electrode is higher than a level of a top surface of the semiconductor substrate.
10 . The semiconductor package of claim 1 , further comprising:
an interposer substrate between the substrate and the semiconductor chip; and
a chip stack on the interposer substrate,
wherein the chip stack comprises a plurality of memory chips which are stacked.
11 . The semiconductor package of claim 1 , wherein the dummy chip further comprises a thermally conductive layer on the second surface of the semiconductor substrate.
12 . The semiconductor package of claim 11 , wherein the at least one penetration electrode penetrates the thermally conductive layer.
13 . The semiconductor package of claim 11 , wherein a thickness of the thermally conductive layer is in a range from 10 μm to 100 μm.
14 . The semiconductor package of claim 11 , wherein the thermally conductive layer comprises at least one from among aluminum (Al), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), magnesium oxide (MgO), and silicon carbide (SiC).
15 . The semiconductor package of claim 1 , wherein
the dummy chip comprises a first region and a second region,
the at least one penetration electrode is a plurality of penetration electrodes,
some of the plurality of penetration electrodes are in the first region, and others of the plurality of penetration electrodes are in the second region, and
a number of the plurality of penetration electrodes per unit area in the first region is greater than a number of the plurality of penetration electrodes per unit area in the second region.
16 . The semiconductor package of claim 1 , wherein the semiconductor chip comprises a first width in a second direction parallel to the top surface of the semiconductor chip,
the dummy chip comprises a second width in the second direction, and
the first width is smaller than the second width.
17 . The semiconductor package of claim 1 , wherein the semiconductor chip comprises a first width in a second direction parallel to the top surface of the semiconductor chip,
the dummy chip has a second width in the second direction, and
the first width is larger than the second width.
18 . A semiconductor package, comprising:
a substrate;
a semiconductor chip on the substrate;
an interposer substrate between the substrate and the semiconductor chip;
a chip stack on the interposer substrate;
a dummy chip on the semiconductor chip; and
a first protection layer between the semiconductor chip and the dummy chip,
wherein the chip stack is spaced apart from the semiconductor chip in a first direction parallel to a top surface of the semiconductor chip,
wherein the dummy chip comprises:
a semiconductor substrate comprises a first surface and a second surface, opposite to the first surface, the first surface being closer than the second surface to the semiconductor chip;
a second protection layer on the first surface; and
a penetration electrode penetrating the semiconductor substrate and the second protection layer,
wherein the penetration electrode is spaced apart from the semiconductor chip in a second direction perpendicular to the top surface of the semiconductor chip, and
wherein the first protection layer is in contact with the second protection layer.
19 . A semiconductor package, comprising:
a first sub-package; and
a second sub-package on the first sub-package,
wherein the first sub-package comprises:
a lower redistribution substrate;
a first semiconductor chip on the lower redistribution substrate;
a dummy chip on the first semiconductor chip; and
a first protection layer between the first semiconductor chip and the dummy chip,
wherein the dummy chip comprises:
a semiconductor substrate comprising a first surface and a second surface, opposite to the first surface, the first surface being closer than the second surface to the first semiconductor chip;
a second protection layer on the first surface; and
a penetration electrode penetrating the semiconductor substrate and the second protection layer,
wherein the penetration electrode is spaced apart from the first semiconductor chip in a first direction perpendicular to a top surface of the first semiconductor chip,
wherein the first protection layer is in contact with the second protection layer, and
wherein the second sub-package comprises:
an upper redistribution substrate;
a second semiconductor chip on the upper redistribution substrate; and
an upper substrate between the upper redistribution substrate and the second semiconductor chip.
20 . The semiconductor package of claim 19 , wherein
the first semiconductor chip is a logic chip, and
the second semiconductor chip is a memory chip.