IP Library › Granted Patent US 12666967

Granted Patent B2

US 12666967 · App. 18/242,906 · Granted Jun 23, 2026

Seal rings for a wide band-gap semiconductor layer stack

Inventors: Ian McCallum-Cook (Burlington, VT); Mark Levy (Williston, VT); Zhong-Xiang He (Essex Junction, VT)

Assignee: GlobalFoundries U.S. Inc.

H10W42/00 H10W74/134 H10W74/147 H10D30/475 H10D62/8503 H10W74/43

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Quick Facts

Patent No.: US 12666967
App. No.: 18/242,906
Granted: Jun 23, 2026
Kind: B2

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Abstract

Structures including a wide band-gap semiconductor layer stack and methods of forming such structures. The structure comprises a layer stack on a substrate and a first dielectric layer on the layer stack. The layer stack includes semiconductor layers that comprise a wide band-gap semiconductor material. A seal ring includes a trench that penetrates through the first dielectric layer and the layer stack to the substrate, a second dielectric layer that lines the trench, and a conductor layer including first and second portions inside the trench. The trench surrounds portions of the layer stack and the first dielectric layer. The second dielectric layer includes a first portion disposed between the first portion of the conductor layer and the portion of the layer stack, and the second dielectric layer includes a second portion disposed between the second portion of the conductor layer and the portion of the first dielectric layer.

Claims (47)

1 . A structure comprising:

a substrate;

a layer stack on the substrate, the layer stack including a plurality of semiconductor layers, and each semiconductor layer comprising a wide band-gap semiconductor material;

a first dielectric layer on the layer stack;

a seal ring including a trench that penetrates through the first dielectric layer and the layer stack to the substrate, a second dielectric layer that lines the trench, and a conductor layer including a first portion and a second portion inside the trench, the trench surrounding a portion of the layer stack and a portion of the first dielectric layer, the second dielectric layer including a first portion disposed between the first portion of the conductor layer and the portion of the layer stack, and the second dielectric layer including a second portion disposed between the second portion of the conductor layer and the portion of the first dielectric layer;

a device structure including a gate on the portion of the layer stack;

a contact in the portion of the first dielectric layer; and

a back-end-of-line stack including a first metallization level over the portion of the first dielectric layer, the first metallization level including a first interlayer dielectric layer,

wherein the first interlayer dielectric layer includes an interconnect that is coupled by the contact to the gate of the device structure, and the second dielectric layer includes a third portion providing the first interlayer dielectric layer.

2 . The structure of claim 1 wherein the conductor layer comprises copper.

3 . The structure of claim 1 wherein the conductor layer comprises tungsten.

4 . The structure of claim 1 wherein the seal ring further includes a third dielectric layer that lines the trench, the third dielectric layer including a first portion disposed between the first portion of the second dielectric layer and the portion of the layer stack, and the third dielectric layer including a second portion is disposed between the second portion of the second dielectric layer and the portion of the first dielectric layer.

5 . The structure of claim 4 wherein the second dielectric layer comprises silicon dioxide, and the third dielectric layer comprises silicon nitride.

6 . The structure of claim 4 wherein the seal ring further includes a fourth dielectric layer, the fourth dielectric layer includes a first portion disposed between the first portion of the second dielectric layer and the first portion of the conductor layer, and the fourth dielectric layer includes a second portion disposed between the second portion of the second dielectric layer and the second portion of the conductor layer.

7 . The structure of claim 6 wherein the second dielectric layer comprises silicon dioxide, and the third dielectric layer and the fourth dielectric layer comprise silicon nitride.

8 . The structure of claim 1 wherein the interconnect and the conductor layer comprise different materials.

9 . The structure of claim 1 wherein the interconnect and the conductor layer comprise the same material.

10 . The structure of claim 1 wherein the back-end-of-line stack includes a second metallization level, and the second metallization level includes a second interlayer dielectric layer dielectric layer over the seal ring and the first interlayer dielectric layer.

11 . The structure of claim 1 wherein the second portion of the conductor layer has a planar top surface.

12 . The structure of claim 1 further comprising:

a device structure including a gate on the portion of the layer stack,

wherein the portion of the first dielectric layer is disposed over the device structure, and the second dielectric layer continuously coats the first dielectric layer and the trench.

13 . A structure comprising:

a substrate;

a layer stack on the substrate, the layer stack including a plurality of semiconductor layers, and each semiconductor layer comprising a wide band-gap semiconductor material;

a first dielectric layer on the layer stack; and

wherein the trench has an outer sidewall and an inner sidewall between the outer sidewall and the portion of the layer stack, the outer sidewall and the inner sidewall fully surround the portion of the layer stack, and the second dielectric layer includes a third portion between the first portion of the conductor layer and the substrate at the bottom of the trench.

14 . The structure of claim 13 wherein the trench has a bottom in the substrate that extends between the outer sidewall and the inner sidewall, and the trench is tapered with a width that decreases with decreasing distance from the bottom of the trench.

15 . The structure of claim 13 wherein the first portion of the conductor adjoins the substrate at the bottom of the trench.

16 . The structure of claim 13 further comprising:

a device structure including a gate on the portion of the layer stack; and

a contact in the portion of the first dielectric layer, the contact coupled to the gate of the device structure.

17 . The structure of claim 13 further comprising:

a device structure including a gate on the portion of the layer stack;

a contact in the portion of the first dielectric layer; and

a back-end-of-line stack including a metallization level over the portion of the first dielectric layer, the metallization level including an interlayer dielectric layer,

wherein the second dielectric layer includes a third portion providing the interlayer dielectric layer, and the interlayer dielectric layer of the back-end-of-line stack includes an interconnect that is coupled by the contact to the gate of the device structure.

18 . The structure of claim 13 wherein the interconnect and the conductor layer comprise the same material.

19 . The structure of claim 13 wherein the conductor layer comprises copper.

20 . A method comprising:

forming a layer stack on a substrate, wherein the layer stack includes a plurality of semiconductor layers, and each semiconductor layer comprises a wide band-gap semiconductor material;

forming a first dielectric layer on the layer stack;

forming a seal ring including a trench that penetrates through the first dielectric layer and the layer stack to the substrate, a second dielectric layer that lines the trench, and a conductor layer including a first portion and a second portion inside the trench, wherein the trench surrounds a portion of the layer stack and a portion of the first dielectric layer, the second dielectric layer includes a first portion disposed between the first portion of the conductor layer and the portion of the layer stack, and the second dielectric layer includes a second portion disposed between the second portion of the conductor layer and the portion of the first dielectric layer;

forming a device structure including a gate on the portion of the layer stack;

forming a contact in the portion of the first dielectric layer; and

forming a back-end-of-line stack including a first metallization level over the portion of the first dielectric layer, wherein the first metallization level includes an interlayer dielectric layer, the interlayer dielectric layer includes an interconnect that is coupled by the contact to the gate of the device structure, and the second dielectric layer includes a third portion providing the first interlayer dielectric layer.