Semiconductor device and method forming same
Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.
1 . A method of manufacturing a semiconductor device comprising:
forming a redistribution structure over a core substrate;
forming a first resist layer over the redistribution structure;
patterning the first resist layer to expose a portion of the redistribution structure and a portion of the core substrate;
forming a second resist layer over the first resist layer;
patterning the second resist layer, wherein the patterning the second resist layer removes the second resist layer from over the portion of the redistribution structure, the portion of the core substrate, and portions of the second resist layer forming a stress-release structure;
adhering a chip to the core substrate; and
dispensing an underfill covering the stress-release structure.
2 . The method of claim 1 , wherein the patterning the second resist layer is performed by exposing first portions of the second resist layer to an energy source and removing second portions of the second resist layer that were not exposed to the energy source.
3 . The method of claim 1 , wherein the stress-release structure is adjacent to a corner of the chip and further comprises a plurality of stress-release-blocks.
4 . The method of claim 3 , wherein the plurality of stress-release-blocks extend away from the corner of the chip in a linear line and a space between each of the plurality of stress-release-blocks is at least 5 microns.
5 . The method of claim 3 , wherein the plurality of stress-release-blocks extend away from the corner of the chip, the plurality of stress-release-blocks diminishing in size as the plurality of stress-release-blocks extend further away from the corner of the chip.
6 . The method of claim 1 , wherein the stress-release structure further comprises an “L” shaped pattern.
7 . The method of claim 1 , wherein the stress-release structure is formed along a diagonal of the chip in a plan view.
8 . A method of manufacturing a semiconductor device, the method comprising:
forming a first resist layer over a first substrate, the first substrate having a first conductive feature;
patterning the first resist layer to form a first patterned resist layer, the first patterned resist layer having a first opening exposing a portion of the first conductive feature;
forming a second resist layer over the first patterned resist layer;
patterning the second resist layer to form a second patterned resist layer, wherein the second patterned resist layer comprises one or more stress-release structures on an upper surface of the first patterned resist layer;
attaching a semiconductor structure to the first substrate, a conductive pad of the semiconductor structure being electrically coupled to the first conductive feature; and
dispensing an underfill between the semiconductor structure and the first substrate, the underfill covering the one or more stress-release structures.
9 . The method of claim 8 , wherein the first substrate comprises a core substrate and a first redistribution structure on a first side of the core substrate, the first conductive feature being a conductive feature of the first redistribution structure.
10 . The method of claim 8 , wherein at least one of the one or more stress-release structures is positioned adjacent to each corner of the semiconductor structure in a plan view.
11 . The method of claim 8 , wherein a plurality of stress-release structures is positioned in each corner of the semiconductor structure in a plan view.
12 . The method of claim 8 , wherein the underfill completely covers each of the one or more stress-release structures.
13 . The method of claim 8 , wherein the one or more stress-release structures are laterally spaced apart from sidewalls of the semiconductor structure.
14 . The method of claim 8 , wherein the one or more stress-release structures have a thermal decomposition temperature greater than 300° C.
15 . The method of claim 8 , wherein the one or more stress-release structures comprise a first stress-release structure and a second stress-release structure adjacent a first corner of the semiconductor structure, wherein the first stress-release structure is closer to the semiconductor structure than the second stress-release structure, wherein a height of the first stress-release structure is greater than a height of the second stress-release structure.
16 . A method comprising:
forming a first polymer layer over a device substrate;
forming a first dielectric block on an upper surface of the first polymer layer;
attaching a semiconductor structure to the device substrate; and
dispensing an underfill material between the semiconductor structure and the device substrate, wherein the underfill material encapsulates an upper surface and all sidewalls of the first dielectric block.
17 . The method of claim 16 , wherein the device substrate comprises a core substrate and a redistribution structure.
18 . The method of claim 16 , wherein the first dielectric block is positioned along a line passing through diagonal corners of the semiconductor structure in a plan view.
19 . The method of claim 16 , wherein the first dielectric block is one dielectric block of a plurality of dielectric blocks, wherein each of the dielectric blocks of the plurality of dielectric blocks is positioned near a respective corner of the semiconductor structure in a plan view.
20 . The method of claim 16 , wherein forming the first dielectric block comprises forming a plurality of dielectric blocks adjacent a first corner of the semiconductor structure in a plan view, wherein the plurality of dielectric blocks extends away from the first corner of the semiconductor structure, a height of the dielectric blocks of the plurality of dielectric blocks decreases as the plurality of dielectric blocks extend away from the first corner of the semiconductor structure.