Semiconductor package
A semiconductor package includes a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface, a chip pad located on the first surface and including a conductive layer, a support pad positioned on the first surface, spaced apart from the chip pad and including an insulating layer, a support bump connected to the support pad, a wiring substrate disposed to face the semiconductor substrate, a support bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the support bump, and a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad.
1 . A semiconductor package comprising:
a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface;
a chip pad disposed on the first surface of the semiconductor substrate and comprising a conductive layer;
a support pad disposed on the first surface of the semiconductor substrate, spaced apart from the chip pad, and comprising an insulating layer;
a support bump connected to the support pad;
a wiring substrate disposed to face the semiconductor substrate;
a support bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the support bump; and
a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad.
2 . The semiconductor package of claim 1 , wherein:
the first surface of the semiconductor substrate is an active surface,
the second surface of the semiconductor substrate is an inactive surface, and
the support pad comprises a photo sensitive resist layer.
3 . The semiconductor package of claim 1 , wherein the dummy area comprises a conductive layer.
4 . The semiconductor package of claim 1 , wherein the dummy area comprises an insulating layer.
5 . The semiconductor package of claim 1 , wherein the support BOT pad is part of a linear trace pattern extending in a first direction in a plane on the wiring substrate.
6 . The semiconductor package of claim 5 , wherein:
the linear trace pattern comprises a plurality of linear trace patterns, and
the plurality of linear trace patterns are separated from each other by a plurality of separation areas.
7 . The semiconductor package of claim 1 , wherein:
the support BOT pad includes a first support BOT pad and a second support BOT pad,
the first support BOT pad is a first part of a first linear trace pattern extending in a first direction in a plane on the wiring substrate, and
the second support BOT pad is a second part of the first linear trace pattern, the second part being spaced apart from the first part.
8 . The semiconductor package of claim 1 , wherein:
the support BOT pad includes a first support BOT pad and a second support BOT pad,
the first support BOT pad is part of a first linear trace pattern extending in a first direction in a plane on the wiring substrate
the second support BOT pad is part of a second linear trace pattern that is spaced apart from the first linear trace pattern in a second direction perpendicular to the first direction and that extends in the first direction in a plane on the wiring substrate, and
the first linear trace pattern and the second linear trace pattern are connected by connection patterns in the second direction.
9 . The semiconductor package of claim 1 , wherein the support BOT pad is part of a circular trace pattern forming a closed loop in a plane on the wiring substrate.
10 . The semiconductor package of claim 1 , wherein:
the support BOT pad includes a first support BOT pad and a second support BOT pad,
the first support BOT pad is part of a first circular trace pattern forming a first closed loop in a plane on the wiring substrate, and
the second support BOT pad is part of a second circular trace pattern forming a second closed loop in a plane on the wiring substrate.
11 . A semiconductor package comprising:
a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface;
a chip pad disposed on the first surface of the semiconductor substrate and comprising a conductive layer;
a support pad disposed on the first surface of the semiconductor substrate, spaced apart from the chip pad, and comprising an insulating layer;
a conductive bump connected to the chip pad;
a support bump connected to the support pad;
a wiring substrate disposed to face the semiconductor substrate;
a wiring bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the conductive bump;
a support BOT pad disposed on the wiring substrate and bonded to the support bump; and
a dummy area spaced apart from the support BOT pad on the wiring substrate and comprising a conductive layer,
wherein the conductive bump is electrically connected to a wiring layer formed on the wiring substrate, and the support bump is not electrically connected to the wiring layer.
12 . The semiconductor package of claim 11 , wherein the support BOT pad is part of a linear trace pattern extending in a first direction in a plane on the wiring substrate.
13 . The semiconductor package of claim 11 , wherein:
the support BOT pad includes a first support BOT pad and a second support BOT pad,
the first support BOT pad is a first part of a first linear trace pattern extending in a first direction in a plane on the wiring substrate, and
the second support BOT pad is a second part of the first linear trace pattern spaced apart from the first part.
14 . The semiconductor package of claim 11 , wherein:
the support BOT pad includes a first support BOT pad and a second support BOT pad,
the first support BOT pad is part of a first linear trace pattern extending in a first direction in a plane on the wiring substrate, and
the second support BOT pad is part of a second linear trace pattern that is spaced apart from the first linear trace pattern in a second direction perpendicular to the first direction and that extends in the first direction in a plane on the wiring substrate.
15 . The semiconductor package of claim 11 , wherein the support BOT pad is part of a circular trace pattern forming a closed loop in a plane on the wiring substrate.
16 . A semiconductor package comprising:
a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface;
a chip pad disposed on the first surface of the semiconductor substrate and comprising a conductive layer;
a support pad disposed on the first surface of the semiconductor substrate, spaced apart from the chip pad, and comprising an insulating layer;
a conductive bump connected to the chip pad;
a support bump connected to the support pad;
a wiring substrate disposed to face the semiconductor substrate;
a wiring bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the conductive bump;
a support BOT pad disposed on the wiring substrate and bonded to the support bump; and
a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad,
wherein the support BOT pad is part of a first linear trace pattern extending in a first direction in a plane on the wiring substrate, and
wherein the dummy area is spaced apart from the first linear trace pattern and surrounds the first linear trace pattern in a plane on the wiring substrate.
17 . The semiconductor package of claim 16 , wherein the dummy area comprises a conductive layer or an insulating layer.
18 . The semiconductor package of claim 16 , further comprising a second linear trace pattern that is spaced apart from the first linear trace pattern in a second direction perpendicular to the first direction and that extends in the first direction in a plane on the wiring substrate,
wherein the dummy area is spaced apart from the first linear trace pattern and the second linear trace pattern and surrounds the first linear trace pattern and the second linear trace pattern in a plane on the wiring substrate.
19 . The semiconductor package of claim 18 , further comprising a connection pattern disposed to connect the first linear trace pattern to the second linear trace pattern,
wherein the first linear trace pattern, the second linear trace pattern, and the connection pattern form a closed loop.
20 . The semiconductor package of claim 18 , wherein:
the support bump includes a plurality of support bumps,
the support BOT pad includes a plurality of support BOT pads, and
the plurality of support BOT pads are spaced apart from each other and bonded to the plurality of support bumps, and the plurality of support BOT pads are formed on the first linear trace pattern and the second linear trace pattern.