Semiconductor device, method of manufacturing semiconductor device, and method of disposing alignment mark
There is provided a semiconductor device including a first chip and a second chip bonded to the first chip. The first chip includes a first alignment mark provided in a first region of a bonding surface and a plurality of first dummy pads provided in a second region of the bonding surface different from the first region. The second chip includes a second alignment mark provided on the bonding surface corresponding to the first alignment mark and a plurality of second dummy pads provided in a region of the bonding surface different from the second alignment mark. A coverage of the first alignment mark in the first region is substantially the same as the coverage of the first dummy pads in the second region.
1 . A semiconductor device comprising:
a first chip; and
a second chip bonded to the first chip, wherein
the first chip includes:
a first alignment mark disposed in a first region of a bonding surface, and
a plurality of first dummy pads disposed in a second region of the bonding surface different from the first region,
the second chip includes:
a second alignment mark disposed on the bonding surface corresponding to the first alignment mark, and
a plurality of second dummy pads disposed in a region of the bonding surface different from the second alignment mark, and
wherein a coverage of the first alignment mark in the first region is substantially the same as a coverage of the first dummy pads in the second region.
2 . The semiconductor device according to claim 1 , wherein
the first alignment mark includes a plurality of alignment pads, and
the plurality of alignment pads in the first region has a contrast different from that of the plurality of first dummy pads in the second region.
3 . The semiconductor device according to claim 1 , wherein
the first alignment mark includes a plurality of alignment pads, and
one of the alignment pads and the first dummy pads is larger in size and larger in pitch than another.
4 . The semiconductor device according to claim 3 , wherein
a size of the alignment pad is smaller than a size of the first dummy pad, and
a pitch between the alignment pads is smaller than a pitch between the first dummy pads.
5 . The semiconductor device according to claim 3 , wherein
a size of the alignment pad is larger than a size of the first dummy pad, and
a pitch between the alignment pads is larger than a pitch between the first dummy pads.
6 . The semiconductor device according to claim 5 , wherein
the first dummy pads are further disposed between the alignment pads.
7 . The semiconductor device according to claim 1 , wherein
the first alignment mark includes a plurality of alignment pads, and
at least one of the alignment pads and the first dummy pads are located in a triangular lattice shape.
8 . The semiconductor device according to claim 1 , wherein
the first alignment mark includes a plurality of alignment pads, and
a shape of the alignment pads is different from the shape of the first dummy pad.
9 . The semiconductor device according to claim 1 , wherein
the first alignment mark includes a plurality of alignment pads,
the plurality of alignment pads are arranged in the first region for each first pattern composed of two or more of the alignment pads,
the plurality of first dummy pads are located in the second region for each second pattern composed of two or more of the first dummy pads, and
a coverage of the alignment pads in the first pattern is substantially the same as the coverage of the first dummy pads in the second pattern.
10 . The semiconductor device according to claim 9 , wherein
the plurality of first patterns are located side by side sequentially.
11 . The semiconductor device according to claim 1 , wherein
for each position where a predetermined range is moved by a predetermined fraction of one side of the predetermined range, a coverage of the first alignment mark and the first dummy pads with respect to the predetermined range is in a range of 25±20%, and
the predetermined range has a size that is a product of a predetermined number and a maximum long side of the first dummy pads.
12 . The semiconductor device according to claim 1 , wherein
the first alignment mark is asymmetric with respect to an axis parallel to the bonding surface.
13 . The semiconductor device according to claim 1 , wherein
the first chip includes:
a first semiconductor element, and
a first columnar electrode electrically connected to the first semiconductor element and penetrating through the first chip,
the second chip includes:
a second semiconductor element, and
a second columnar electrode electrically connected to the second semiconductor element and penetrating through the second chip, and
the first columnar electrode is electrically connected to the second columnar electrode.
14 . A method of manufacturing a semiconductor device, the method comprising:
forming a first alignment mark in a first region and a plurality of first dummy pads in a second region different from the first region on a first surface of a first chip;
forming a second alignment mark corresponding to the first alignment mark and a plurality of second dummy pads in a region different from the second alignment mark on a second surface of a second chip;
bonding the first surface of the first chip and the second surface of the second chip together based on the first alignment mark and the second alignment mark; and forming the first alignment mark and the plurality of first dummy pads such that a coverage of the first alignment mark in the first region is substantially the same as a coverage of the first dummy pads in the second region.
15 . A method of disposing an alignment mark, the method comprising:
forming a first recess portion in a first region of an insulating film of a first chip and forming a second recess portion in a second region of the insulating film;
forming a conductor on the insulating film and inside the first recess portion and the second recess portion; and
forming a plurality of first dummy pads in the first region and a first alignment mark in the second region by polishing the conductor until the insulating film is exposed; and
forming the first recess portion and the second recess portion such that a coverage of the first alignment mark in the first region is substantially the same as a coverage of the first dummy pads in the second region.
16 . The semiconductor device according to claim 1 , wherein the first alignment mark has a substantially L shape.
17 . The semiconductor device according to claim 1 , wherein the plurality of first dummy pads are formed of metal.
18 . The semiconductor device according to claim 1 , wherein each of the plurality of first dummy pads has a substantially square shape.
19 . The semiconductor device according to claim 1 , wherein the plurality of first dummy pads are arranged in a lattice.
20 . The semiconductor device according to claim 2 , wherein each of the plurality of alignment pads has a substantially square shape.