IP Library Granted Patent US 12666977
Granted Patent B2
US 12666977 · App. 17/558,304 · Granted Jun 23, 2026

Methods, systems, apparatus, and articles of manufacture for integrated circuit package substrates with high aspect ratio through glass vias

Inventors: Veronica Strong (Hillsboro, OR); Aleksandar Aleksov (Chandler, AZ); Georgios Dogiamis (Chandler, AZ); Telesphor Kamgaing (Chandler, AZ); Neelam Prabhu Gaunkar (Chandler, AZ); Brandon Rawlings (Chandler, AZ)
Assignee: Intel Corporation
H10W70/611H10W70/095H10W70/635H10W90/00H10W70/66H10W72/823H10W90/22
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Quick Facts
Patent No.
US 12666977
App. No.
17/558,304
Granted
Jun 23, 2026
Kind
B2
Abstract

Methods, systems, apparatus, and articles of manufacture are disclosed for integrated circuit package substrates with high aspect ratio through glass vias. An example microelectronic package including a glass substrate including a via, the via including a high aspect ratio. The example microelectronic package further including a seed layer extending substantially evenly along an inner wall of the via.

Claims (38)

1 . A microelectronic package comprising:

a glass substrate including a via, the via including an aspect ratio greater than a six to one ratio, a first portion of the via connects with a second portion of the via, the first portion and the second portion extending through the glass substrate at different first and second angles such that there is a change in direction along a length of the via, the first portion having a first width and the second portion having a second width, the second width different from the first width; and

a seed layer extending substantially evenly along an inner wall of the via.

2 . The microelectronic package of claim 1 , including an adhesion layer extending substantially evenly along the inner wall of the via, the adhesion layer separating the seed layer from the inner wall of the via.

3 . The microelectronic package of claim 1 , wherein the via is a first via, and the glass substrate includes a second via different than the first via, the second via extending through the glass substrate at a third angle, the third angle different than the first angle and different than the second angle.

4 . The microelectronic package of claim 1 , wherein the via is a first via of a plurality of vias in the glass substrate, different ones of the plurality of vias extending through the glass substrate at different angles.

5 . The microelectronic package of claim 1 , including a first plane of metal on a first side of the glass substrate and a second plane of metal on a second side of the glass substrate, the first side opposite the second side, the first plane of metal offset relative to the second plane of metal so as to be non-overlapping in a direction perpendicular to the first plane of metal, the via to extend from the first plane of metal to the second plane of metal.

6 . The microelectronic package of claim 1 , wherein the seed layer is a metal seed layer, the metal seed layer including at least one of copper, ruthenium, cobalt, or tungsten.

7 . The microelectronic package of claim 1 , wherein the via is plated with a metal, the metal including copper.

8 . The microelectronic package of claim 7 , including a first die mounted directly to a first side of the glass substrate and a second die mounted directly to a second side of the glass substrate, the first die and the second die connected to the via.

9 . The microelectronic package of claim 1 , wherein the via is filled with at least one of a dielectric plug or a magnetic plug.

10 . An apparatus comprising:

a glass substrate having a first side and a second side opposite the first side, the glass substrate including a first channel extending between the first and second sides at a first angle, the glass substrate including a second channel extending between the first and second sides at a second angle different than the first angle, the glass substrate including hairpin filters, a first one of the hairpin filters is connected to the first channel, the first channel including:

a first portion extending through the glass substrate substantially parallel to the first side of the glass substrate, and

a second portion extending through the glass substrate at a non-perpendicular and non-parallel angle to the first side of the glass substrate; and

a metal seed layer on a first surface of the first channel and on a second surface of the second channel, the metal seed layer on the first surface having a first thickness, the metal seed layer on the second surface having a second thickness, the first thickness the same as the second thickness.

11 . The apparatus of claim 10 , wherein the first channel and the second channel include aspect ratios of at least a ten to one ratio.

12 . The apparatus of claim 10 , including an adhesion layer on the first and second surfaces of the first and second channels, the adhesion layer on the first surface having a third thickness, the adhesion layer on the second surface having a fourth thickness, the third thickness the same as the fourth thickness, the adhesion layer between the metal seed layer and the first and second channels.

13 . The apparatus of claim 10 , wherein the first and second channels are different ones of a plurality of channels in an array in the glass substrate, successive ones of the plurality of channels including a plurality of first ends and a plurality of second ends, a first pitch of the plurality of first ends is less than a second pitch of the plurality of second ends.

14 . The apparatus of claim 10 , wherein the first channel intersects with the second channel at a location spaced apart from and between the first and second sides of the glass substrate.

15 . The apparatus of claim 10 , the first channel including a third portion extending through the glass substrate substantially parallel to the first portion, the first portion connected to a first side of the second portion and the third portion connected to a second side of the second portion.

16 . A microelectronic package comprising:

a glass substrate having a first surface and a second surface opposite the first surface, the glass substrate including a via and a hairpin filter connected to the via, a first portion of the via extending through the glass substrate substantially parallel to the first surface of the glass substrate, a second portion of the via extending through the glass substrate at a non-perpendicular and non-parallel angle to the first surface of the glass substrate;

a first layer on a wall of the via, the first layer including at least one of titanium, tungsten, or nitrogen; and

a second layer on the first layer, the second layer including ruthenium.

17 . The microelectronic package of claim 16 , wherein the via has an aspect ratio of greater than six to one.

18 . The microelectronic package of claim 16 , wherein the via is a first via, and the glass substrate includes a second via different than the first via, the first via extending through the glass substrate at a first angle, the second via extending through the glass substrate at a second angle, the first angle different than the second angle.

19 . The microelectronic package of claim 16 , wherein the via is a first via of a plurality of vias in the glass substrate, different ones of the plurality of vias extending through the glass substrate at different angles.

20 . The microelectronic package of claim 16 , wherein the via is a first via and the microelectronic package includes:

a first plane of metal on a first side of the glass substrate;

a second plane of metal on a second side of the glass substrate, the first side opposite the second side, the first plane of metal offset relative to the second plane of metal so as to be non-overlapping in a direction perpendicular to the first plane of metal; and

a second via to extend from the first plane of metal to the second plane of metal at a non-perpendicular angle relative to the first and second planes.

21 . The microelectronic package of claim 16 , wherein the via is filled with at least one of a dielectric material or a magnetic material.

22 . A microelectronic package comprising:

a glass substrate including:

a via having an aspect ratio greater than a six to one ratio, a first portion of the via connects with a second portion of the via, the first portion and the second portion extending through the glass substrate at different angles to result in a first change in direction along a length of the via, and

a first surface and a second surface opposite the first surface, a third portion of the via connects with the second portion of the via, the second and third portions of the via extending through the glass substrate at different angles to result in a second change in direction in the via, the first portion extending from the second portion to at least one of the first surface or the second surface, the third portion extending from the second portion to at least one of the first surface or the second surface, the second portion spaced apart from the first surface and spaced apart from the second surface; and

a seed layer extending substantially evenly along an inner wall of the via.