Stress-reduced package substrate and method of forming the same

Inventors: Huayan Wang (Campbell, CA); Seungbae Park (Vestal, NY); Gamal Refai-Ahmed (Santa Clara, CA); Suresh Ramalingam (Fremont, CA); Jaspreet Singh Gandhi (San Jose, CA); Yu Hsiang Sun (Hsin Chu, TW); Scott Mccann (Sunnyvale, CA)

Assignee: XILINX, INC.

H10W70/65 H10W70/05 H10W70/685

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12666981
App. No.: 17/142,926
Granted: Jun 23, 2026
Kind: B1

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Disclosed herein is a package substrate and a method for fabricating the same. In one example, a package substrate includes a core having an outer edge and a first plurality of first interconnect layers disposed on the core. The first plurality of interconnect layers disposed on the core include an outermost dielectric layer disposed farthest from the core. The outermost dielectric layer has an edge that is recessed from the edge of the core.

Claims (30)

1 . A package substrate comprising:

a core having an outer edge and containing no IC dies; and

a first plurality of interconnect layers disposed on the core and forming at least a portion of the package substrate, wherein at least two of the first plurality of interconnect layers have edges that are progressively recessed from the outer edge of the core to define a stairstep profile constructed during buildup of the first plurality of interconnect layers, the first plurality of interconnect layers disposed on the core including an outermost dielectric layer disposed farthest from the core, the outermost dielectric layer having an edge that is recessed from the edge of the core, wherein the first plurality of interconnect layers further comprises:

an underlying dielectric layer disposed between the outermost dielectric layer and the core, the underlying dielectric layer having an edge that is disposed between the edge of the core and the edge of the outermost dielectric layer; and

a second plurality of interconnect layers disposed on a side of the core opposite the first plurality of interconnect layers, wherein at least two of the second plurality of interconnect layers have edges that are progressively recessed from the outer edge of the core to define a complementary stairstep profile constructed during buildup of the second plurality of interconnect layers.

2 . The package substrate of claim 1 , wherein the outer edge of the core forms an arc at a corner of the package substrate.

3 . The package substrate of claim 2 , wherein the edge of the outermost dielectric layer is recessed from the outer edge of the core at the corner of the package substrate.

4 . The package substrate of claim 2 , wherein the arc includes a plurality of scallops having an orientation substantially perpendicular to a plane of the core.

5 . The package substrate of claim 1 , wherein at least two dielectric layers of the first plurality of interconnect layers are recessed from the edge of the core.

6 . The package substrate of claim 1 , wherein one or more of the first plurality of interconnect layers has a chamfered edge.

7 . The package substrate of claim 1 , wherein one or more of the first plurality of interconnect layers has a radiused edge.

8 . The package substrate of claim 1 , wherein the recess is at a midpoint of a side of the package substrate.

9 . The package substrate of claim 1 , wherein the recess is along adjacent sides of the package substrate.

10 . The package substrate of claim 1 wherein the second plurality of interconnect layers are equal in number to the first plurality of interconnect layers.

11 . The package substrate of claim 1 , wherein edges of the underlying dielectric layer form an acute angle with a top surface of the outermost dielectric layer.

12 . The package substrate of claim 1 , wherein edges of the underlying dielectric layer form a radius.

13 . An integrated circuit device comprising:

an IC die having solid state circuitry; and

a package substrate comprising:

a core having an outer edge and a plurality of vias and containing no IC dies; and

a first plurality of interconnect layers disposed on the core and forming at least a portion of the package substrate, wherein at least two of the first plurality of interconnect layers have edges that are progressively recessed from the outer edge of the core to define a stairstep profile constructed during buildup of the first plurality of interconnect layers, the first plurality of interconnect layers including routings that electrically couple the plurality of vias of the core to the solid state circuitry of the IC die, the first plurality of interconnect layers disposed on the core including an outermost dielectric layer disposed farthest from the core and having the IC die communicatively and mechanically coupled thereto, the outermost dielectric layer having an edge that is recessed from the edge of the core, wherein the first plurality of interconnect layers further comprises:

14 . The integrated circuit device of claim 13 , wherein the outer edge of the core forms an arc at a corner of the package substrate.

15 . The integrated circuit device of claim 14 , wherein the edge of the outermost dielectric layer is recessed from the outer edge of the core at the corner of the package substrate.

16 . The integrated circuit device of claim 14 , wherein the arc includes a plurality of scallops having an orientation substantially perpendicular to a plane of the core.

17 . The integrated circuit device of claim 13 , wherein at least two dielectric layers of the first plurality of interconnect layers are recessed from the edge of the core.

18 . The integrated circuit device of claim 13 , wherein one or more of the first plurality of interconnect layers has a chamfered edge.

19 . The integrated circuit device of claim 13 , wherein one or more of the first plurality of interconnect layers has a radiused edge.

20 . The package substrate of claim 13 , wherein edges of the underlying dielectric layer form an acute angle with a top surface of the outermost dielectric layer or form a radius.